74HC237
3-to-8 line decoder, demultiplexer with address latches
Rev. 7 — 29 January 2016
Product data sheet
1. General description
The 74HC237 is a high-speed Si-gate CMOS device and is pin compatible with low-power
Schottky TTL (LSTTL). The 74HC237 is specified in compliance with JEDEC
standard no. 7A.
The 74HC237 is a 3-to-8 line decoder, demultiplexer with latches at the three address
inputs (An). The 74HC237 essentially combines the 3-to-8 decoder function with a 3-bit
storage latch. When the latch is enabled (LE = LOW), the 74HC237 acts as a 3-to-8 active
LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present
at the inputs before this transition, is stored in the latches. Further address changes are
ignored as long as LE remains HIGH. The output enable input (E1 and E2) controls the
state of the outputs independent of the address inputs or latch operation. All outputs are
HIGH unless E1 is LOW and E2 is HIGH. The 74HC237 is ideally suited for implementing
non-overlapping decoders in 3-state systems and strobes (stored address) applications in
bus-oriented systems.
2. Features and benefits
Combines 3-to-8 decoder with 3-bit latch
Multiple input enable for easy expansion or independent controls
Active HIGH mutually exclusive outputs
Low-power dissipation
ESD protection:
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Temperature range
74HC237D
74HC237DB
40 C
to +125
C
40 C
to +125
C
Name
SO16
SSOP16
Description
plastic small outline package; 16 leads; body width
3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
Version
SOT109-1
SOT338-1
Type number Package
NXP Semiconductors
74HC237
3-to-8 line decoder, demultiplexer with address latches
4. Functional diagram
Fig 1.
Functional diagram
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
74HC237
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 7 — 29 January 2016
2 of 17
NXP Semiconductors
74HC237
3-to-8 line decoder, demultiplexer with address latches
Fig 4.
Logic diagram
5. Pinning information
5.1 Pinning
Fig 5.
Pin configuration SO16
Fig 6.
Pin configuration SSOP16
74HC237
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 7 — 29 January 2016
3 of 17
NXP Semiconductors
74HC237
3-to-8 line decoder, demultiplexer with address latches
5.2 Pin description
Table 2.
Symbol
A0 to A2
LE
E1
E2
Y0 to Y7
GND
V
CC
Pin description
Pin
1, 2, 3
4
5
6
8
16
Description
data input
latch enable input (active LOW)
data enable input 1 (active LOW)
data enable input 2 (active HIGH)
ground (0 V)
supply voltage
15, 14, 13, 12, 11, 10, 9, 7 output
6. Functional description
Table 3.
Enable
LE
H
X
X
L
E1
L
H
X
L
E2
H
X
L
H
Function table
Input
A0
X
X
X
L
H
L
H
L
H
L
H
[1]
Output
A1
X
X
X
L
L
H
H
L
L
H
H
A2
X
X
X
L
L
L
L
H
H
H
H
Y0
stable
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
Y1
Y2
Y3
Y4
Y5
Y6
Y7
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
74HC237
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 7 — 29 January 2016
4 of 17
NXP Semiconductors
74HC237
3-to-8 line decoder, demultiplexer with address latches
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to (V
CC
+ 0.5 V)
Min
0.5
-
-
-
-
-
65
Max
+7
20
20
25
+50
50
+150
500
Unit
V
mA
mA
mA
mA
mA
C
mW
SO16 and SSOP16 packages
[1]
-
For SO16 package: P
tot
derates linearly with 8 mW/K above 70
C.
For SSOP16 package: P
tot
derates linearly with 5.5 mW/K above 60
C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol
V
CC
V
I
V
O
T
amb
t/V
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
Min
2.0
0
0
40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
Unit
V
V
V
C
ns/V
ns/V
ns/V
74HC237
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 7 — 29 January 2016
5 of 17
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