Micron Confidential and Proprietary
2Gb: x8, x16 NAND Flash Memory
Features
NAND Flash Memory
MT29F2G08ABAEAH4, MT29F2G08ABAEAWP, MT29F2G08ABBEAH4,
MT29F2G08ABBEAHC, MT29F2G16ABAEAWP, MT29F2G16ABBEAH4
MT29F2G16ABBEAHC
Features
• Open NAND Flash Interface (ONFI) 1.0-compliant
1
• Single-level cell (SLC) technology
• Organization
– Page size x8: 2112 bytes (2048 + 64 bytes)
– Page size x16: 1056 words (1024 + 32 words)
– Block size: 64 pages (128K + 4K bytes)
– Plane size: 2 planes x 1024 blocks per plane
– Device size: 2Gb: 2048 blocks
• Asynchronous I/O performance
–
t
RC/
t
WC: 20ns (3.3V), 25ns (1.8V)
• Array performance
– Read page: 25µs
3
– Program page: 200µs (TYP: 1.8V, 3.3V)
3
– Erase block: 700µs (TYP)
• Command set: ONFI NAND Flash Protocol
• Advanced command set
– Program page cache mode
4
– Read page cache mode
4
– One-time programmable (OTP) mode
– Two-plane commands
4
– Interleaved die (LUN) operations
– Read unique ID
– Block lock (1.8V only)
– Internal data move
• Operation status byte provides software method for
detecting
– Operation completion
– Pass/fail condition
– Write-protect status
• Ready/Busy# (R/B#) signal provides a hardware
method of detecting operation completion
• WP# signal: Write protect entire device
• First block (block address 00h) is valid when ship-
ped from factory with ECC. For minimum required
ECC, see Error Management.
• Block 0 requires 1-bit ECC if PROGRAM/ERASE cy-
cles are less than 1000
• RESET (FFh) required as first command after pow-
er-on
• Alternate method of device initialization (Nand_In-
it) after power up (contact factory)
• Internal data move operations supported within the
plane from which data is read
• Quality and reliability
– Data retention: 10 years
– Endurance: 100,000 PROGRAM/ERASE cycles
• Operating voltage range
– V
CC
: 2.7–3.6V
– V
CC
: 1.7–1.95V
• Operating temperature
– Commercial: 0°C to +70°C
– Industrial (IT): –40ºC to +85ºC
– Automotive Industrial (AIT): –40°C to +85°C
– Automotive (AT): –40°C to +105°C
– Automotive Certified (AAT): –40°C to +105°C
• Package
– 48-pin TSOP type 1, CPL
2
– 63-ball VFBGA
Notes:
1. The ONFI 1.0 specification is available at
www.onfi.org.
2. CPL = Center parting line.
3. See Electrical Specifications – Program/Erase
Characteristics for
t
R_ECC and
t
PROG_ECC
specifications.
4. These commands supported only with ECC
disabled.
PDF: 09005aef83b83f42
m69a_2gb_ecc_nand.pdf - Rev. S 10/16 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
2Gb: x8, x16 NAND Flash Memory
Features
Part Numbering Information
Micron NAND Flash devices are available in different configurations and densities. Verify valid part numbers by
using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type,
visit www.micron.com/products. Contact the factory for devices not found.
Figure 1: Marketing Part Number Chart
MT 29F 2G 08
Micron Technology
Product Family
29F = NAND Flash memory
A
B
A
E
A
WP-
IT
ES :E
Design Revision (shrink)
Production Status
Blank = Production
ES = Engineering sample
MS = Mechanical sample
QS = Qualification sample
Density
2G = 2Gb
Device Width
08 = 8-bit
16 = 16-bit
Special Options
Blank
X = Product longevity program (PLP)
Level
A = SLC
Operating Temperature Range
Blank = Commercial (0°C to +70°C)
IT = Industrial (–40°C to +85°C)
AIT = Automotive Industrial (–40°C to +85°C)
AAT = Automotive Certified (–40°C to +115°C)
AT = Automotive (–40°C to +115°C)
Classification
Mark Die
B
1
nCE
1
RnB
1
I/O Channels
1
Operating Voltage Range
A = 3.3V (2.7–3.6V)
B = 1.8V (1.7–1.95V)
Speed Grade
Blank
Package Code
WP = 48-pin TSOP
HC = 63-ball VFBGA (10.5 x 13 x 1.0mm)
H4 = 63-ball VFBGA (9 x 11 x 1.0mm)
Feature Set
E = Feature set E
Interface
A = Async only
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m69a_2gb_ecc_nand.pdf - Rev. S 10/16 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
2Gb: x8, x16 NAND Flash Memory
Features
Contents
General Description ......................................................................................................................................... 8
Signal Descriptions ........................................................................................................................................... 8
Signal Assignments ........................................................................................................................................... 9
Package Dimensions ....................................................................................................................................... 12
Architecture ................................................................................................................................................... 15
Device and Array Organization ........................................................................................................................ 16
Asynchronous Interface Bus Operation ........................................................................................................... 18
Asynchronous Enable/Standby ................................................................................................................... 18
Asynchronous Commands .......................................................................................................................... 18
Asynchronous Addresses ............................................................................................................................ 20
Asynchronous Data Input ........................................................................................................................... 21
Asynchronous Data Output ......................................................................................................................... 22
Write Protect# ............................................................................................................................................ 23
Ready/Busy# .............................................................................................................................................. 24
Device Initialization ....................................................................................................................................... 28
Command Definitions .................................................................................................................................... 29
Reset Operations ............................................................................................................................................ 32
RESET (FFh) ............................................................................................................................................... 32
Identification Operations ................................................................................................................................ 33
READ ID (90h) ............................................................................................................................................ 33
READ ID Parameter Tables .............................................................................................................................. 34
READ PARAMETER PAGE (ECh) ...................................................................................................................... 36
Parameter Page Data Structure Tables ............................................................................................................. 37
READ UNIQUE ID (EDh) ................................................................................................................................ 41
Feature Operations ......................................................................................................................................... 42
SET FEATURES (EFh) .................................................................................................................................. 43
GET FEATURES (EEh) ................................................................................................................................. 44
Status Operations ........................................................................................................................................... 47
READ STATUS (70h) ................................................................................................................................... 48
READ STATUS ENHANCED (78h) ................................................................................................................ 48
Column Address Operations ........................................................................................................................... 50
RANDOM DATA READ (05h-E0h) ................................................................................................................ 50
RANDOM DATA READ TWO-PLANE (06h-E0h) ............................................................................................ 51
RANDOM DATA INPUT (85h) ...................................................................................................................... 52
PROGRAM FOR INTERNAL DATA INPUT (85h) ........................................................................................... 53
Read Operations ............................................................................................................................................. 55
READ MODE (00h) ..................................................................................................................................... 57
READ PAGE (00h-30h) ................................................................................................................................ 57
READ PAGE CACHE SEQUENTIAL (31h) ...................................................................................................... 58
READ PAGE CACHE RANDOM (00h-31h) .................................................................................................... 59
READ PAGE CACHE LAST (3Fh) .................................................................................................................. 61
READ PAGE TWO-PLANE 00h-00h-30h ....................................................................................................... 62
Program Operations ....................................................................................................................................... 64
PROGRAM PAGE (80h-10h) ......................................................................................................................... 65
PROGRAM PAGE CACHE (80h-15h) ............................................................................................................. 65
PROGRAM PAGE TWO-PLANE (80h-11h) .................................................................................................... 68
Erase Operations ............................................................................................................................................ 70
ERASE BLOCK (60h-D0h) ............................................................................................................................ 70
ERASE BLOCK TWO-PLANE (60h-D1h) ....................................................................................................... 71
Internal Data Move Operations ....................................................................................................................... 72
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m69a_2gb_ecc_nand.pdf - Rev. S 10/16 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
2Gb: x8, x16 NAND Flash Memory
Features
READ FOR INTERNAL DATA MOVE (00h-35h) ............................................................................................. 73
PROGRAM FOR INTERNAL DATA MOVE (85h–10h) ..................................................................................... 74
PROGRAM FOR INTERNAL DATA MOVE TWO-PLANE (85h-11h) ................................................................. 75
Block Lock Feature ......................................................................................................................................... 76
WP# and Block Lock ................................................................................................................................... 76
UNLOCK (23h-24h) .................................................................................................................................... 76
LOCK (2Ah) ................................................................................................................................................ 79
LOCK TIGHT (2Ch) ..................................................................................................................................... 80
BLOCK LOCK READ STATUS (7Ah) .............................................................................................................. 81
One-Time Programmable (OTP) Operations .................................................................................................... 83
Legacy OTP Commands .............................................................................................................................. 83
OTP DATA PROGRAM (80h-10h) ................................................................................................................. 84
RANDOM DATA INPUT (85h) ...................................................................................................................... 85
OTP DATA PROTECT (80h-10) ..................................................................................................................... 86
OTP DATA READ (00h-30h) ......................................................................................................................... 88
Two-Plane Operations .................................................................................................................................... 90
Two-Plane Addressing ................................................................................................................................ 90
Interleaved Die (Multi-LUN) Operations .......................................................................................................... 99
Error Management ........................................................................................................................................ 100
Internal ECC and Spare Area Mapping for ECC ............................................................................................... 102
Electrical Specifications ................................................................................................................................. 104
Electrical Specifications – DC Characteristics and Operating Conditions .......................................................... 106
Electrical Specifications – AC Characteristics and Operating Conditions .......................................................... 108
Electrical Specifications – Program/Erase Characteristics ................................................................................ 111
Asynchronous Interface Timing Diagrams ...................................................................................................... 112
Revision History ............................................................................................................................................ 124
Rev. S – 10/16 ............................................................................................................................................ 124
Rev. R – 04/14 ............................................................................................................................................ 124
Rev. Q – 02/14 ............................................................................................................................................ 124
Rev. P – 08/13 ............................................................................................................................................ 124
Rev. O – 10/12 ............................................................................................................................................ 124
Rev. N – 02/12 ............................................................................................................................................ 124
Rev. M – 01/12 ........................................................................................................................................... 124
Rev. L – 11/11 ............................................................................................................................................ 124
Rev. K – 01/11 ............................................................................................................................................ 124
Rev. J – 12/10 ............................................................................................................................................. 124
Rev. I – 11/10 ............................................................................................................................................. 124
Rev. H – 09/10 ............................................................................................................................................ 125
Rev. G – 08/10 ............................................................................................................................................ 125
Rev. F – 06/10 ............................................................................................................................................ 125
Rev. E – 05/10 ............................................................................................................................................ 125
Rev. D – 03/10 ............................................................................................................................................ 125
Rev. C – 01/10 ............................................................................................................................................ 125
Rev. B – 09/09 ............................................................................................................................................ 125
Rev. A – 07/09 ............................................................................................................................................ 126
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m69a_2gb_ecc_nand.pdf - Rev. S 10/16 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
2Gb: x8, x16 NAND Flash Memory
Features
List of Figures
Figure 1: Marketing Part Number Chart ............................................................................................................ 2
Figure 2: 48-Pin TSOP – Type 1, CPL (Top View) ................................................................................................ 9
Figure 3: 63-Ball VFBGA, x8 (Balls Down, Top View) ........................................................................................ 10
Figure 4: 63-Ball VFBGA, x16 (Balls Down, Top View) ...................................................................................... 11
Figure 5: 48-Pin TSOP – Type 1, CPL ............................................................................................................... 12
Figure 6: 63-Ball VFBGA (10.5mm x 13mm) .................................................................................................... 13
Figure 7: 63-Ball VFBGA (9mm x 11mm) ......................................................................................................... 14
Figure 8: NAND Flash Die (LUN) Functional Block Diagram ............................................................................ 15
Figure 9: Array Organization – MT29F2G08 (x8) .............................................................................................. 16
Figure 10: Array Organization – MT29F2G16 (x16) .......................................................................................... 17
Figure 11: Asynchronous Command Latch Cycle ............................................................................................ 19
Figure 12: Asynchronous Address Latch Cycle ................................................................................................ 20
Figure 13: Asynchronous Data Input Cycles .................................................................................................... 21
Figure 14: Asynchronous Data Output Cycles ................................................................................................. 22
Figure 15: Asynchronous Data Output Cycles (EDO Mode) ............................................................................. 23
Figure 16: READ/BUSY# Open Drain .............................................................................................................. 25
Figure 17:
t
Fall and
t
Rise (3.3V V
CC
) ................................................................................................................ 25
Figure 18:
t
Fall and
t
Rise (1.8V V
CC
) ................................................................................................................ 26
Figure 19: I
OL
vs. Rp (V
CC
= 3.3V V
CC
) .............................................................................................................. 26
Figure 20: I
OL
vs. Rp (1.8V V
CC
) ....................................................................................................................... 27
Figure 21: TC vs. Rp ....................................................................................................................................... 27
Figure 22: R/B# Power-On Behavior ............................................................................................................... 28
Figure 23: RESET (FFh) Operation .................................................................................................................. 32
Figure 24: READ ID (90h) with 00h Address Operation .................................................................................... 33
Figure 25: READ ID (90h) with 20h Address Operation .................................................................................... 33
Figure 26: READ PARAMETER (ECh) Operation .............................................................................................. 36
Figure 27: READ UNIQUE ID (EDh) Operation ............................................................................................... 41
Figure 28: SET FEATURES (EFh) Operation .................................................................................................... 43
Figure 29: GET FEATURES (EEh) Operation .................................................................................................... 44
Figure 30: READ STATUS (70h) Operation ...................................................................................................... 48
Figure 31: READ STATUS ENHANCED (78h) Operation ................................................................................... 49
Figure 32: RANDOM DATA READ (05h-E0h) Operation ................................................................................... 50
Figure 33: RANDOM DATA READ TWO-PLANE (06h-E0h) Operation .............................................................. 51
Figure 34: RANDOM DATA INPUT (85h) Operation ........................................................................................ 52
Figure 35: PROGRAM FOR INTERNAL DATA INPUT (85h) Operation .............................................................. 54
Figure 36: READ PAGE (00h-30h) Operation ................................................................................................... 58
Figure 37: READ PAGE (00h-30h) Operation with Internal ECC Enabled .......................................................... 58
Figure 38: READ PAGE CACHE SEQUENTIAL (31h) Operation ......................................................................... 59
Figure 39: READ PAGE CACHE RANDOM (00h-31h) Operation ....................................................................... 60
Figure 40: READ PAGE CACHE LAST (3Fh) Operation ..................................................................................... 61
Figure 41: READ PAGE TWO-PLANE (00h-00h-30h) Operation ........................................................................ 63
Figure 42: PROGRAM PAGE (80h-10h) Operation ............................................................................................ 65
Figure 43: PROGRAM PAGE CACHE (80h–15h) Operation (Start) ..................................................................... 67
Figure 44: PROGRAM PAGE CACHE (80h–15h) Operation (End) ...................................................................... 67
Figure 45: PROGRAM PAGE TWO-PLANE (80h–11h) Operation ....................................................................... 69
Figure 46: ERASE BLOCK (60h-D0h) Operation .............................................................................................. 70
Figure 47: ERASE BLOCK TWO-PLANE (60h–D1h) Operation .......................................................................... 71
Figure 48: READ FOR INTERNAL DATA MOVE (00h-35h) Operation ................................................................ 73
Figure 49: READ FOR INTERNAL DATA MOVE (00h–35h) with RANDOM DATA READ (05h–E0h) ..................... 73
Figure 50: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled ........................................................ 74
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5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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