(Note 3) ...................................................... –40 to 125°C
Storage Temperature Range ...................... –65 to 125°C
24 23 22 21 20
V
SYS
1
PROG 2
CLPROG 3
CHGOFF 4
BSTOFF 5
V
IN
6
CLN 7
UFD PACKAGE
24-LEAD (4mm
×
5mm) PLASTIC QFN
T
JMAX
= 125°C,
θ
JA
= 43°C/W
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH
LTC4040EUFD#PBF
LTC4040IUFD#PBF
TAPE AND REEL
LTC4040EUFD#TRPBF
LTC4040IUFD#TRPBF
PART MARKING*
4040
4040
PACKAGE DESCRIPTION
TEMPERATURE RANGE
24-Lead (4mm
×
5mm
×
0.75mm) Plastic QFN –40°C to 125°C
24-Lead (4mm
×
5mm
×
0.75mm) Plastic QFN –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
2
4040fa
For more information
www.linear.com/LTC4040
LTC4040
elecTrical characTerisTics
SYMBOL
V
IN
V
BAT
I
INQ
I
BATQ
PARAMETER
Input Voltage Range
Battery Voltage Range (Backup Boost Input)
V
IN
Quiescent Current
BAT Quiescent Current
Normal Mode (V
PFI
= 2V), Battery Charger Timed Out
Shutdown (BSTOFF = CHGOFF=1)
Normal Mode (V
PFI
= 2V), Battery Charger Timed Out
l
Backup Mode (V
IN
= V
PFI
= 0V), No System Load
Shutdown (BSTOFF = CHGOFF = 1)
F2 = 0, F1 = 0, F0 = 0
F2 = 0, F1 = 0, F0 = 1
F2 = 0, F1 = 1, F0 = 0
F2 = 0, F1 = 1, F0 = 1
F2 = 1, F1 = 0, F0 = 0
F2 = 1, F1 = 0, F0 = 1
F2 = 1, F1 = 1, F0 = 0
F2 = 1, F1 = 1, F0 = 1
R
PROG
= 2k
l
l
l
l
l
l
l
l
The
l
denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at T
A
= 25°C. (Note 3) V
IN
= 5V, V
BAT
= 3.6V, R
PROG
= 2k, unless otherwise noted.
CONDITIONS
l
MIN
3.5
2.7
TYP
MAX
5.5
5
UNITS
V
V
µA
µA
µA
µA
µA
V
V
V
V
V
V
V
V
mA
mV
mV
mV
mA/
mA
mA
mV
570
3.5
45
40
1.5
3.42
3.47
3.52
3.57
3.92
3.97
4.02
4.07
950
40
125
3.45
3.50
3.55
3.60
3.95
4.00
4.05
4.10
1000
50
145
800
2500
7
70
3
3.48
3.53
3.58
3.63
3.98
4.03
4.08
4.13
1050
60
165
Battery Charger
V
CHG
BAT Regulated Output Voltage for LiFePO
4
Option (F2 = 0)
BAT Regulated Output Voltage for Li-Ion
Option (F2 = 1)
I
CHG
Regulated Battery Charge Current
V
SYS
-to-V
BAT
Differential Undervoltage
Lockout Threshold (Falling)
V
SYS
-to-BAT Differential Undervoltage
Lockout Threshold (Rising)
V
PROG
h
PROG
I
TRKL
PROG Pin Servo Voltage
Ratio of Battery Current to PROG Pin Current
Trickle Charge Current
PROG Pin Servo Voltage at Trickle Charge
Input Current Limit Threshold Voltage
V
BAT
= 2.5V, R
PROG
= 2k
V
BAT
= 2.5V, R
PROG
= 2k
V
IN
– V
CLN
Ratio of CLPROG Voltage to (V
IN
– V
CLN
)
V
CLN
= V
IN
Threshold Voltage Relative to V
CHG
if F2 = 0 and F1 = 1
Threshold Voltage Relative to V
CHG
All Other Cases
Timer Starts When V
BAT
= V
CHG
F2 = 1 (Li-Ion)
F2 = 0 (LiFePO
4
)
94.2
96.7
3.7
1.85
2.75
0.47
90
1.96
l
125
100
23.5
25
32
300
95
97.5
4.25
2.13
2.85
150
0.54
100
2.25
130
120
3
4.3
95.8
98.3
5
2.5
2.95
0.64
110
2.65
26.5
mV
V/V
nA
%
%
Hours
Hours
V
mV
Hours
mV
MHz
mΩ
mΩ
A
A
CLPROG
V
RECHG
t
TERMINATE
V
LOWBAT
½V
LOWBAT
t
BADBAT
V
C/8
f
OSC(BUCK)
R
P(BUCK)
R
N(BUCK)
I
LIM(BUCK)
Input Current Limit Amplifier Gain
CLN Input Bias Current
Recharge Battery Threshold Voltage
Safety Timer Termination Period
Low Battery Threshold Voltage for Trickle Charge V
BAT
Rising
Low Battery Hysteresis
Bad-Battery Termination Time
End-of-Charge Indication
Step-Down (Buck) Converter Switching
Frequency
High Side Switch On-Resistance
Low Side Switch On-Resistance
PMOS Switch Current Limit
V
BAT
< (V
LOWBAT
− ΔV
LOWBAT
)
PROG Pin Average Voltage
Normal Mode (V
PFI
> 1.21V)
Normal Mode (V
PFI
> 1.21V)
Normal Mode (V
PFI
> 1.21V)
4040fa
For more information
www.linear.com/LTC4040
3
LTC4040
elecTrical characTerisTics
SYMBOL
NTC
V
COLD
V
HOT
V
DIS
I
NTC
V
BSTFB
I
BSTFB
V
SYS
f
OSCBST
I
LIMBST
R
PBST
R
NBST
V
OVSD
V
UVLO
D
MAX
Cold Temperature Fault Threshold Voltage
Hot Temperature Fault Threshold Voltage
NTC Disable Threshold Voltage
NTC Leakage Current
BSTFB Reference Voltage
BSTFB Input Bias Current
Step-up (Boost) Converter Output Voltage
Range
Step-Up Converter Switching Frequency
NMOS Switch Current Limit
Boost High Side Switch On-Resistance
Boost Low Side Switch On-Resistance
V
SYS
Overvoltage Shutdown Threshold
Overvoltage Shutdown Hysteresis
BAT Pin Undervoltage Lockout
BAT Pin Undervoltage Lockout Hysteresis
Maximum Boost Duty Cycle
NMOS Switch Leakage
PMOS Switch Leakage
Reset Comparator
RSTFB Threshold (Falling)
RSTFB Hysteresis
RSTFB Pin Leakage Current
RST
Delay (RSTFB Rising)
Power-Fail Comparator
PFI Input Threshold (Falling Edge)
PFI Input Hysteresis
PFI Pin Leakage Current
PFI Delay to
PFO
PFO
Pin Leakage Current
PFO
Pin Output Low Voltage
Logic Input (CHGOFF, BSTOFF, F0, F1, F2)
V
IL
V
IH
I
IL
I
IH
Logic Low Input Voltage
Logic High Input Voltage
Logic Low Input Leakage
Logic High Input Leakage
l
l
l
l
The
l
denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at T
A
= 25°C. (Note 3) V
IN
= 5V, V
BAT
= 3.6V, R
PROG
= 2k, unless otherwise noted.
PARAMETER
CONDITIONS
Rising Voltage Threshold
Hysteresis
Falling Voltage Threshold
Hysteresis
Falling Threshold
Hysteresis
MIN
75.0
33.4
0.7
–20
0.78
–20
3.5
Backup Mode (V
PFI
< 1.17V)
0.98
5.5
1.125
6.5
75
70
V
SYS
Rising
V
BAT
Falling
5.3
5.5
100
2.45
150
88
BSTOFF = 1, CHGOFF = 1
BSTOFF = 1, CHGOFF = 1
0.72
–50
232
Initiates Backup Mode
V
PFI
= 1.3V
PFI Falling
V
PFO
= 5V
I
PFO
= 5mA
l
TYP
76.5
1.5
34.9
1.73
1.7
50
MAX
78
36.4
2.7
20
UNITS
%V
IN
%V
IN
%V
IN
%V
IN
%V
IN
mV
nA
V
nA
V
MHz
A
mΩ
mΩ
Backup Mode Boost Switching Regulator
0.8
0.82
20
5
1.33
7.5
5.7
2.6
91
V
mV
V
mV
%
µA
µA
1
1
0.74
20
0.76
50
V
mV
nA
ms
V
RSTFB
= 0.9V
1.17
–100
1.19
30
1.21
100
V
mV
nA
µs
µA
mV
0.5
10
65
0.4
1.2
–1
–1
1
1
V
V
µA
µA
4
4040fa
For more information
www.linear.com/LTC4040
LTC4040
elecTrical characTerisTics
SYMBOL
PARAMETER
Pin Leakage Current
Pin Output Low Voltage
Overvoltage Protection
V
OV(CUTOFF)
Overvoltage Protection Threshold
V
OVGT
IGATE Output Voltage Active
Rising Threshold, R
OVSNS
= 6.2k
Input Voltage < V
OV(CUTOFF)
5V Through 6.2k Into OVSNS, I
IGATE
= 1µA
V
OVSNS
= 5V
BSTOFF = H, CHGOFF = H
C
IGATE
= 2.2nF
8
6.1
6.4
1.88
•
V
OVSNS
8.6
40
25
3.5
6.7
12
V
V
V
µA
µA
ms
Open-Drain Output (CHRG,
RST, FAULT)
V = 5V
I = 5mA
65
1
µA
mV
The
l
denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at T
A
= 25°C. (Note 3) V
IN
= 5V, V
BAT
= 3.6V, R
PROG
= 2k, unless otherwise noted.
CONDITIONS
MIN
TYP
MAX
UNITS
V
OVGT(LOAD)
IGATE Voltage Under Load
I
OVSNSQ
OVSNS Quiescent Current
OVSNS Quiescent Current at Shutdown
IGATE Time to Reach Regulation
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3:
The LTC4040E is tested under pulsed load conditions such that
T
J
≈ T
A
. The LTC4040E is guaranteed to meet performance specifications
from 0°C to 85°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process control. The
LTC4040I is guaranteed over the full –40°C to 125°C operating junction
temperature range. The junction temperature (T
J
in °C) is calculated from
the ambient temperature (T
A
, in °C) and power dissipation (P
D
, in watts)
according to the formula:
T
J
= T
A
+ (P
D
•
θ
JA
)
where the package thermal impedance
θ
JA
= 43°C/W.
Note that the maximum ambient temperature consistent with these
specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal resistance and
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