High Performance E
2
CMOS
®
In-System Programmable Logic
FEATURES
x
High-performance, E
2
CMOS 3.3-V & 5-V CPLD families
x
Flexible architecture for rapid logic designs
ispMACH
™
4A CPLD Family
x
x
x
x
x
x
x
x
— Excellent First-Time-Fit
TM
and refit feature
— SpeedLocking
TM
performance for guaranteed fixed timing
— Central, input and output switch matrices for 100% routability and 100% pin-out retention
High speed
— 5.0ns t
PD
Commercial and 7.5ns t
PD
Industrial
— 182MHz f
CNT
32 to 512 macrocells; 32 to 768 registers
44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages
Flexible architecture for a wide range of design styles
— D/T registers and latches
— Synchronous or asynchronous mode
— Dedicated input registers
— Programmable polarity
— Reset/ preset swapping
Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— JTAG (IEEE 1149.1) compliant for boundary scan testing
— 3.3-V & 5-V JTAG in-system programming
— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system designs
— Programmable pull-up or Bus-Friendly
TM
inputs and I/Os
— Hot-socketing
— Programmable security bit
— Individual output slew rate control
Advanced E
2
CMOS process provides high-performance, cost-effective solutions
Supported by ispDesignEXPERT
TM
software for rapid logic development
— Supports HDL design methodologies with results optimized for ispMACH 4A
— Flexibility to adapt to user requirements
— Software partnerships that ensure customer success
Lattice and third-party hardware programming support
— LatticePRO
TM
software for in-system programmability support on PCs and automated test
equipment
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,
and System General
Publication#
ISPM4A
Amendment/0
Rev:
D
Issue Date:
August 2000
Table 1. ispMACH 4A Device Features
3.3 V Devices
Feature
Macrocells
User I/O options
t
PD
(ns)
f
CNT
(MHz)
t
COS
(ns)
t
SS
(ns)
Static Power (mA)
JTAG Compliant
PCI Compliant
5 V Devices
Feature
Macrocells
User I/O options
t
PD
(ns)
f
CNT
(MHz)
t
COS
(ns)
t
SS
(ns)
Static Power (mA)
JTAG Compliant
PCI Compliant
M4A5-32
2
32
32
5.0
182
4.0
3.0
20
Yes
Yes
M4A5-64
2
64
32
5.5
167
4.0
3.5
25
Yes
Yes
M4A5-96
2
96
48
5.5
167
4.0
3.5
40
Yes
Yes
M4A5-128
2
128
64
5.5
167
4.0
3.5
55
Yes
Yes
M4A5-192
1
192
96
6.0
160
4.5
3.5
74
Yes
Yes
M4A5-256
2
256
128
6.5
154
5.0
3.5
110
Yes
Yes
M4A3-32
2
32
32
5.0
182
4.0
3.0
20
Yes
Yes
M4A3-64
2
64
32/64
1
5.5
167
4.0
3.5
25/52
1
Yes
Yes
M4A3-96
2
96
48
5.5
167
4.0
3.5
40
Yes
Yes
M4A3-128
2
128
64
5.5
167
4.0
3.5
55
Yes
Yes
M4A3-192
2
192
96
6.0
160
4.5
3.5
85
Yes
Yes
M4A3-256
256
128
2
/160
1
/192
1
5.5
3
167
4.0
3.5
110
2
/150
1
Yes
Yes
M4A3-384
2
384
160/192
6.5
154
4.5
3.5
149/155
Yes
Yes
M4A3-512
1
512
160/192/256
7.5
125
5.5
5.0
179
Yes
Yes
Notes:
1. Advance information. Please contact a Lattice sales representative for details on availability.
2. Preliminary information.
3. M4A3-256/128 available now in 5.5ns. Contact factory for availability of 7.5ns M4A3-256/160 and M4A3-256/192
2
ispMACH 4A Family
GENERAL DESCRIPTION
The ispMACH
™
4A family from Lattice offers an exceptionally flexible architecture and delivers
a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products
and software tools. The overall benefits for users are a guaranteed and predictable CPLD
solution, faster time-to-market, greater flexibility and lower cost. The ispMACH 4A devices offer
densities ranging from 32 to 512 macrocells with 100% utilization and 100% pin-out retention.
The ispMACH 4A families offer 5-V (M4A5-xxx) and 3.3-V (M4A3-xxx) operation.
ispMACH 4A products are 5-V or 3.3-V in-system programmable through the JTAG (IEEE Std.
1149.1) interface. JTAG boundary scan testing also allows product testability on automated test
equipment for device connectivity.
All ispMACH 4A family members deliver First-Time-Fit and easy system integration with pin-out
retention after any design change and refit. For both 3.3-V and 5-V operation, ispMACH 4A
products can deliver guaranteed fixed timing as fast as 5.0 ns t
PD
and 182 MHz f
CNT
through the
SpeedLocking feature when using up to 20 product terms per output (Table 2).
Table 2. ispMACH 4A Speed Grades
Speed Grade
Device
M4A3-32
3
M4A5-32
3
M4A3-64/32
3
M4A5-64/32
3
M4A3-64/64
2
M4A3-96
3
M4A5-96
3
M4A3-128
3
M4A5-128
3
M4A3-192
3
M4A5-192
2
M4A3-256/128
3
M4A5-256/128
3
M4A3-256/192
2
M4A3-256/160
2
M4A3-384
2
M4A3-512
2
Notes:
1. C = Commercial,
C
C
C
-5
C
C
C
C
C
C
C
C
-55
-6
-65
-7
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C
C
-10
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
-12
I
I
I
I
I
I
I
I
I
C, I
C, I
I
I
-14
I = Industrial
2. Advance information. Please contact a Lattice sales representative for details on availability.
3. Preliminary information.
ispMACH 4A Family
3
The ispMACH 4A family offers 20 density-I/O combinations in Thin Quad Flat Pack (TQFP),
Plastic Quad Flat Pack (PQFP), Plastic Leaded Chip Carrier (PLCC), Ball Grid Array (BGA), fine-
pitch BGA (fpBGA), and chip-array BGA (caBGA) packages ranging from 44 to 388 pins (Table
3). It also offers I/O safety features for mixed-voltage designs so that the 3.3-V devices can accept
5-V inputs, and 5-V devices do not overdrive 3.3-V inputs. Additional features include Bus-
Friendly inputs and I/Os, a programmable power-down mode for extra power savings and
individual output slew rate control for the highest speed transition or for the lowest noise
transition.
Table 3. ispMACH 4A Package and I/O Options (Number of I/Os and dedicated inputs in Table)
3.3 V Devices
Package
44-pin PLCC
44-pin TQFP
48-pin TQFP
100-pin TQFP
100-pin PQFP
100-ball caBGA
144-pin TQFP
144-ball fpBGA
208-pin PQFP
256-ball fpBGA
256-ball BGA
388-ball fpBGA
5 V Devices
Package
44-pin PLCC
44-pin TQFP
48-pin TQFP
100-pin TQFP
100-pin PQFP
144-pin TQFP
208-pin PQFP
256-ball BGA
M4A5-32
2
32+2
32+2
32+2
M4A5-64
2
32+2
32+2
32+2
48+8
64+6
64+6
96+16
128+14
128+14
M4A5-96
2
M4A5-128
2
M4A5-192
1
M4A5-256
2
M4A3-32
2
32+2
32+2
32+2
M4A3-64
32+2
2
32+2
2
32+2
2
64+6
1
48+8
64+6
2
64+6
2
64+6
1
96+16
2
96+16
1
128+14
2
, 160
1
128+14
2
, 192
1
128+14
2
160
192
192
256
160
192
M4A3-96
2
M4A3-128
M4A3-192
M4A3-256
M4A3-384
1
M4A3-512
1
Note:
1. Advance information. Please contact a Lattice sales representative for details on availability.
2. Preliminary information.
4
ispMACH 4A Family
FUNCTIONAL DESCRIPTION
The fundamental architecture of ispMACH 4A devices (Figure 1) consists of multiple, optimized
PAL
®
blocks interconnected by a central switch matrix. The central switch matrix allows
communication between PAL blocks and routes inputs to the PAL blocks. Together, the PAL
blocks and central switch matrix allow the logic designer to create large designs in a single
device instead of having to use multiple devices.
The key to being able to make effective use of these devices lies in the interconnect schemes.
In the ispMACH 4A architecture, the macrocells are flexibly coupled to the product terms
through the logic allocator, and the I/O pins are flexibly coupled to the macrocells due to the
output switch matrix. In addition, more input routing options are provided by the input switch
matrix. These resources provide the flexibility needed to fit designs efficiently.
PAL Block
4
Clock
Generator
Clock/Input
Pins
Note 3
Note 2
Central Switch Matrix
Logic
Array
Input
Switch
Matrix
Logic 16
Output/
Allocator
Buried
with XOR
Macrocells
16
16
8
Note 1
Dedicated
Input Pins
16
PAL Block
PAL Block
I/O Cells
33/
34/
36
Output Switch Matrix
I/O
Pins
I/O
Pins
I/O
Pins
17466G-001
Figure 1. ispMACH 4A Block Diagram and PAL Block Structure
Notes:
1. 16 for ispMACH 4A devices with 1:1 macrocell-I/O cell ratio (see next page).
2. Block clocks do not go to I/O cells in M4A(3,5)-32/32.
3. M4A(3,5)-192, M4A(3,5)-256, M4A3-384, and M4A3-512 have dedicated clock pins which cannot be used as inputs and do
not connect to the central switch matrix.
ispMACH 4A Family
5
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