Low Skew 1 to 4 Clock Buffer
551S
DATASHEET
Description
The 551S is a low cost, high-speed single input to four output
clock buffer.
The
551S
has best in class Additive Phase Jitter
of sub 50fsec.
IDT makes many non-PLL and PLL based low skew output
devices as well as Zero Delay Buffers to synchronize clocks.
Contact IDT for all of your clocking needs.
Features
•
•
•
•
•
•
•
•
•
•
•
Low additive phase jitter RMS: 50fs
Extremely low skew outputs (50ps)
Low cost clock buffer
Packaged in 8-pin SOIC and 8-pin DFN, Pb-free
Input/Output clock frequency up to 200 MHz
Non-inverting output clock
Ideal for networking clocks
Operating Voltages: 1.8V to 3.3V
Output Enable mode tri-states outputs
Advanced, low power CMOS process
Extended temperature range (-40°C to +105°C)
Block Diagram
Q1
Q2
ICLK
Q3
Q4
Output Enable
551S REVISION A 03/18/15
1
©2015 Integrated Device Technology, Inc.
551S DATASHEET
Pin Assignment
I CLK
Q1
Q2
Q3
1
2
3
4
8
7
6
5
OE
VDD
GND
Q4
ICLK
Q1
Q2
Q3
1
2
3
4
8-pin DFN
8
7
6
5
OE
VDD
GND
Q4
8 Pi n ( 150 mi l ) SOI C
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
ICLK
Q1
Q2
Q3
Q4
GND
VDD
OE
Pin
Type
Input
Output
Output
Output
Output
Power
Power
Input
Clock output 1.
Clock output 2.
Clock output 3.
Clock output 4.
Connect to ground.
Pin Description
Clock input. Internal pull-up resistor.
Connect +1.8V, +2.5V or +3.3V.
Output Enable. Tri-states outputs when low. Internal pull-up resistor.
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01F should be
connected between VDD on pin 7 and GND on pin 6, as close to the device as possible. A 33 series terminating resistor may
be used on each clock output if the trace is longer than 1 inch.
LOW SKEW 1 TO 4 CLOCK BUFFER
2
REVISION A 03/18/15
551S DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 551S. These ratings, which are standard values
for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended
operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature, Extended
Storage Temperature
Junction Temperature
Soldering Temperature
Rating
3.465
V
-0.5 V to
3.465
V
-40 to +105C
-65 to +150C
125C
260C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature, extended
Power Supply Voltage (measured in respect to GND)
Min.
-40
+1.71
Typ.
–
Max.
+105
+3.465
Units
C
V
REVISION A 03/18/15
3
LOW SKEW 1 TO 4 CLOCK BUFFER
551S DATASHEET
DC Electrical Characteristics
VDD=1.8 V ±5%
,
Ambient temperature -40° to +105°C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage, ICLK
Input Low Voltage, ICLK
Input High Voltage, OE
Input Low Voltage, OE
Output High Voltage
Output Low Voltage
Operating Supply Current
Nominal Output Impedance
Input Capacitance
Notes: 1. Nominal switching threshold is VDD/2.
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
IDD
Z
O
C
IN
OE pin
I
OH
= -10 mA
I
OL
= 10 mA
Note 1
Note 1
Conditions
Min.
1.71
0.7xVDD
0.7xVDD
1.3
Typ.
Max.
1.89
1.89
0.3xVDD
VDD
0.3xVDD
0.35
Units
V
V
V
V
V
V
V
mA
pF
No load, 135 MHz
13
17
5
VDD=2.5 V ±5%
,
Ambient temperature -40° to +105°C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage, ICLK
Input Low Voltage, ICLK
Input High Voltage, OE
Input Low Voltage, OE
Output High Voltage
Output Low Voltage
Operating Supply Current
Nominal Output Impedance
Input Capacitance
Notes: 1. Nominal switching threshold is VDD/2.
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
IDD
Z
O
C
IN
OE pin
I
OH
= -16 mA
I
OL
= 16 mA
Note 1
Note 1
Conditions
Min.
2.375
0.7xVDD
0.7xVDD
1.8
Typ.
Max.
2.625
2.625
0.3xVDD
VDD
0.3xVDD
0.5
Units
V
V
V
V
V
V
V
mA
pF
No load, 135 MHz
18
17
5
VDD=3.3 V ±5%
,
Ambient temperature -40° to +105°C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage, ICLK
Input Low Voltage, ICLK
Input High Voltage, OE
Input Low Voltage, OE
Output High Voltage
Output Low Voltage
Operating Supply Current
Nominal Output Impedance
Input Capacitance
Notes: 1. Nominal switching threshold is VDD/2.
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
IDD
Z
O
C
IN
OE pin
I
OH
= -25 mA
I
OL
= 25 mA
Note 1
Note 1
Conditions
Min.
3.135
0.7xVDD
0.7xVDD
2.2
Typ.
Max.
3.465
3.465
0.3xVDD
VDD
0.3xVDD
0.7
Units
V
V
V
V
V
V
V
mA
pF
No load, 135 MHz
22
17
5
LOW SKEW 1 TO 4 CLOCK BUFFER
4
REVISION A 03/18/15
551S DATASHEET
AC Electrical Characteristics
VDD=1.8V ±5%
, Ambient Temperature -40° to +105°C, unless stated otherwise
Parameter
Output Frequency
Output Clock Rise Time
Output Clock Fall Time
Propagation Delay
Buffer Additive Phase Jitter, RMS
Output to Output Skew
Start-up Time
Output Enable Time
Output Disable Time
t
START-UP
t
EN
t
DIS
t
OR
t
OF
Symbol
0.36 to 1.44 V
1.44 to 0.36V
Conditions
5pF load, Note 4
Min.
Typ.
0.6
0.6
Max.
200
1.0
1.0
4
0.05
65
2
3
3
Units
MHz
ns
ns
ns
ps
ps
ms
cycles
cycles
135 MHz, Note 1
125MHz, Integration range: 12kHz–20MHz
Rising edges at VDD/2, Note 2
Part start-up time for valid outputs after VDD
ramp-up
C
L
< 5pF
C
L
< 5pF
1.5
2
0.03
50
VDD=2.5V ±5%
, Ambient Temperature -40° to +105°C, unless stated otherwise
Parameter
Output Frequency
Output Clock Rise Time
Output Clock Fall Time
Propagation Delay
Buffer Additive Phase Jitter, RMS
Output to Output Skew
Start-up Time
Output Enable Time
Output Disable Time
t
START-UP
t
EN
t
DIS
t
OR
t
OF
Symbol
0.5 to 2.0V
2.0 to 0.5V
Conditions
5pF load, Note 4
Min.
Typ.
0.6
0.6
Max.
200
1.0
1.0
4.5
0.05
65
2
3
3
Units
MHz
ns
ns
ns
ps
ps
ms
cycles
cycles
135 MHz, Note 1
125MHz, Integration range: 12kHz–20MHz
Rising edges at VDD/2, Note 2
Part start-up time for valid outputs after VDD
ramp-up
C
L
< 5pF
C
L
< 5pF
1.8
2.5
0.035
50
VDD=3.3 V ±5%
, Ambient Temperature -40° to +105°C, unless stated otherwise
Parameter
Output Frequency
Output Clock Rise Time
Output Clock Fall Time
Propagation Delay
Buffer Additive Phase Jitter, RMS
Output to Output Skew
Start-up Time
Output Enable Time
Output Disable Time
t
START-UP
t
EN
t
DIS
t
OR
t
OF
Symbol
0.66 to 2.64V
2.64 to 0.66V
Conditions
5pF load, Note 4
Min.
Typ.
0.6
0.6
Max.
200
1.0
1.0
4
0.05
65
2
3
3
Units
MHz
ns
ns
ns
ps
ps
ms
cycles
cycles
135 MHz, Note 1
125MHz, Integration range: 12kHz–20MHz
Rising edges at VDD/2, Note 2
Part start-up time for valid outputs after VDD
ramp-up
C
L
< 5pF
C
L
< 5pF
1.5
2
0.037
50
Notes:
1. With rail to rail input clock.
2. Between any 2 outputs with equal loading.
3. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock generators.
4. With external series resistor of 33 positioned close to each output pin.
REVISION A 03/18/15
5
LOW SKEW 1 TO 4 CLOCK BUFFER
嵌入式系统
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