FM28V100
1-Mbit (128 K × 8) F-RAM Memory
1-Mbit (128 K × 8) F-RAM Memory
Features
■
■
■
32-pin thin small outline package (TSOP) Type I
Restriction of hazardous substances (RoHS) compliant
1-Mbit ferroelectric random access memory (F-RAM) logically
organized as 128 K × 8
14
❐
High-endurance 100 trillion (10 ) read/writes
❐
151-year data retention (see the
Data Retention and
Endurance
table)
❐
NoDelay™ writes
❐
Page mode operation to 30 ns cycle time
❐
Advanced high-reliability ferroelectric process
SRAM compatible
❐
Industry-standard 128 K × 8 SRAM pinout
❐
60-ns access time, 90-ns cycle time
Superior to battery-backed SRAM modules
❐
No battery concerns
❐
Monolithic reliability
❐
True surface mount solution, no rework steps
❐
Superior for moisture, shock, and vibration
Low power consumption
❐
Active current 7 mA (typ)
❐
Standby current 90
A
(typ)
Low-voltage operation: V
DD
= 2.0 V to 3.6 V
Industrial temperature: –40
C
to +85
C
Functional Overview
The FM28V100 is a 128 K × 8 nonvolatile memory that reads and
writes similar to a standard SRAM. A ferroelectric random
access memory or F-RAM is nonvolatile, which means that data
is retained after power is removed. It provides data retention for
over 151 years while eliminating the reliability concerns,
functional disadvantages, and system design complexities of
battery-backed SRAM (BBSRAM). Fast write timing and high
write endurance make the F-RAM superior to other types of
memory.
The FM28V100 operation is similar to that of other RAM devices
and therefore, it can be used as a drop-in replacement for a
standard SRAM in a system. Read and write cycles may be
triggered by chip enable or simply by changing the address. The
F-RAM memory is nonvolatile due to its unique ferroelectric
memory process. These features make the FM28V100 ideal for
nonvolatile memory applications requiring frequent or rapid
writes.
The device is available in a 32-pin TSOP I surface mount
package. Device specifications are guaranteed over the
industrial temperature range –40 °C to +85 °C.
For a complete list of related documentation, click
here.
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Logic Block Diagram
Address Latch
A 2-0
...
A 16-0
Row Decoder
A 16-3
128 K x 8
F-RAM Array
CE 1, CE 2
WE
OE
Control
Logic
...
Column Decoder
I/O Latch & Bus Driver
DQ 7-0
Cypress Semiconductor Corporation
Document Number: 001-86202 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 12, 2015
FM28V100
Contents
Pinout ................................................................................ 3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
Memory Operation ....................................................... 4
Read Operation ........................................................... 4
Write Operation ........................................................... 4
Page Mode Operation ................................................. 4
Pre-charge Operation .................................................. 4
SRAM Drop-In Replacement ....................................... 5
Maximum Ratings ............................................................. 6
Operating Range ............................................................... 6
DC Electrical Characteristics .......................................... 6
Data Retention and Endurance ....................................... 7
Capacitance ...................................................................... 7
Thermal Resistance .......................................................... 7
AC Test Conditions .......................................................... 7
AC Switching Characteristics ......................................... 8
SRAM Read Cycle ...................................................... 8
SRAM Write Cycle ....................................................... 9
Power Cycle Timing ....................................................... 12
Functional Truth Table ................................................... 13
Ordering Information ...................................................... 14
Ordering Code Definitions ......................................... 14
Package Diagrams .......................................................... 15
Acronyms ........................................................................ 16
Document Conventions ................................................. 16
Units of Measure ....................................................... 16
Document History Page ................................................. 17
Sales, Solutions, and Legal Information ...................... 18
Worldwide Sales and Design Support ....................... 18
Products .................................................................... 18
PSoC® Solutions ...................................................... 18
Cypress Developer Community ................................. 18
Technical Support ..................................................... 18
Document Number: 001-86202 Rev. *E
Page 2 of 18
FM28V100
Pinout
Figure 1. 32-pin TSOP I pinout
A
11
A
9
A
8
A
13
WE
CE
2
A
15
V
DD
[1]
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-pin TSOP I
(x 8)
Top view
(not to scale)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A
10
CE
1
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
V
SS
DQ
2
DQ
1
DQ
0
A
0
A
1
A
2
A
3
Pin Definitions
Pin Name
A
16
–A
0
DQ
7
–DQ
0
WE
I/O Type
Input
Description
Address inputs:
The 17 address lines select one of 131,072 bytes in the F-RAM array. The lowest two
address lines A
2
–A
0
may be used for page mode read and write operations.
Write Enable:
A write cycle begins when WE is asserted. The rising edge causes the FM28V100 to write
the data on the DQ bus to the F-RAM array. The falling edge of WE latches a new column address for
page mode write cycles.
Chip Enable:
The device is selected and a new memory access begins on the falling edge of CE
1
(while
CE
2
is HIGH) or the rising edge of CE
2
(while CE
1
is LOW). The entire address is latched internally at
this point. The CE
2
pin is pulled up internally. Subsequent changes to the A
2
–A
0
address inputs allow
page mode operation.
Output Enable:
When OE is LOW, the FM28V100 drives the data bus when the valid read data is
available. Deasserting OE HIGH tristates the DQ pins.
Ground for the device. Must be connected to the ground of the system.
No connect. This pin is not connected to the die.
Input/Output
Data I/O Lines:
8-bit bidirectional data bus for accessing the F-RAM array.
Input
CE
1
, CE
2
Input
OE
V
SS
V
DD
NC
Input
Ground
No connect
Power supply Power supply input to the device.
Note
1. Reserved for address A
17
on 2-Mbit device.
Document Number: 001-86202 Rev. *E
Page 3 of 18
FM28V100
the device is activated with the chip enable. In this case, the
device begins the memory cycle as a write. The FM28V100 will
not drive the data bus regardless of the state of OE as long as
WE is LOW. Input data must be valid when the device is
deselected with a chip enable. In a WE-controlled write, the
memory cycle begins when the device is activated with a chip
enable. The WE signal falls some time later. Therefore, the
memory cycle begins as a read. The data bus will be driven if OE
is LOW; however, it will be HI-Z when WE is asserted LOW. The
chip enable and WE controlled write timing cases are shown in
the
page 11.
In the
Figure 8 on page 11
diagram, the data bus is
shown as a HI-Z condition while the chip is write-enabled and
before the required setup time. Although this is drawn to look like
a mid-level voltage, it is recommended that all DQ pins comply
with the minimum V
IH
/V
IL
operating levels.
Write access to the array begins on the falling edge of WE after
the memory cycle is initiated. The write access terminates on the
deassertion of WE or CE
1
or CE
2
, whichever comes first. A valid
write operation requires the user to meet the access time
specification before deasserting WE or chip enable. The data
setup time indicates the interval during which data cannot
change before the end of the write access.
Unlike other nonvolatile memory technologies, there is no write
delay with F-RAM. Because the read and write access times of
the underlying memory are the same, the user experiences no
delay through the bus. The entire memory operation occurs in a
single bus cycle. Data polling, a technique used with EEPROMs
to determine if a write is complete, is unnecessary.
Device Operation
The FM28V100 is a byte-wide F-RAM memory logically
organized as 131,072 × 8 and accessed using an
industry-standard parallel interface. All data written to the part is
immediately nonvolatile with no delay. The device offers page
mode operation, which provides high-speed access to
addresses within a page (row). Access to a different page
requires that either chip enable transitions LOW or the upper
address (A
16
–A
3
) changes. See the
Functional Truth Table on
page 13
for a complete description of read and write modes.
Memory Operation
Users access 131,072 memory locations, each with 8 data bits
through a parallel interface. The F-RAM array is organized as
16,384 rows and each row has eight column locations, which
allow fast access in page mode operation. When an initial
address is latched by the falling edge of CE
1
(while CE
2
is HIGH),
or the rising edge of CE
2
(while CE
1
is LOW), subsequent
column locations may be accessed without the need to toggle
chip enable. When chip enable pin is deasserted HIGH, a
pre-charge operation begins. Writes occur immediately at the
end of the access with no delay. The WE pin must be toggled for
each write operation. The write data is stored in the nonvolatile
memory array immediately, which is a feature unique to F-RAM
called NoDelay writes.
Read Operation
A read operation begins on the falling edge of CE
1
(while CE
2
is
HIGH), or the rising edge of CE
2
(while CE
1
is LOW). The chip
enable initiated access causes the address to be latched and
starts a memory read cycle if WE is HIGH. Data becomes
available on the bus after the access time is met. When the
address is latched and the access completed, a new access to
a random location (different row) may begin while both chip
enables are still active. The minimum cycle time for random
addresses is t
RC
. Note that unlike SRAMs, the FM28V100's chip
enable-initiated access time is faster than the address access
time.
The FM28V100 will drive the data bus when OE is asserted LOW
and the memory access time is met. If OE is asserted after the
memory access time is met, the data bus will be driven with valid
data. If OE is asserted before completing the memory access,
the data bus will not be driven until valid data is available. This
feature minimizes supply current in the system by eliminating
transients caused by invalid data being driven to the bus. When
OE is deasserted HIGH, the data bus will remain in a HI-Z state.
Page Mode Operation
The FM28V100 provides the user fast access to any data within
a row element. Each row has eight column-address locations
(bytes). Address inputs A
2
–A
0
define the column address to be
accessed. An access can start anywhere within a row and other
column locations may be accessed without the need to toggle
the chip enable pins. For fast access reads, after the first data
byte is driven to the bus, the column address inputs A
2
–A
0
may
be changed to a new value. A new data byte is then driven to the
DQ pins. For fast access writes, the first write pulse defines the
first write access. While the device is selected (both chip enables
asserted), a subsequent write pulse along with a new column
address provides a page mode write access.
Pre-charge Operation
The pre-charge operation is an internal condition in which the
memory state is prepared for a new access. Pre-charge is
user-initiated by driving at least one of the chip enable signals to
an inactive state. The chip enable must remain inactive at least
the minimum pre-charge time, t
PC
.
Pre-charge is also activated by changing the upper addresses,
A
16
–A
3
. The current row is first closed before accessing the new
row. The device automatically detects an upper order address
change, which starts a pre-charge operation. The new address
is latched and the new read data is valid within the t
AA
address
access time; see
Figure 4 on page 10.
A similar sequence occurs
for write cycles; see
Figure 9 on page 11.
The rate at which
Page 4 of 18
Write Operation
In the FM28V100, writes occur in the same interval as reads. The
FM28V100 supports both chip enable and WE controlled write
cycles. In both cases, the address is latched on the falling edge
of CE
1
(while CE
2
is HIGH), or the rising edge of CE
2
(while CE
1
is LOW).
In a chip enable-controlled write, the WE signal is asserted
before beginning the memory cycle. That is, WE is LOW when
Document Number: 001-86202 Rev. *E
FM28V100
random addresses can be issued is t
RC
and t
WC
, respectively.
Note that if CE
1
is tied to ground and CE2 tied to V
DD
, the user
must be sure WE is not LOW at power-up or power-down events.
If the chip is enabled and WE is LOW during power cycles, data
will be corrupted.
Figure 3
shows a pull-up resistor on WE, which
will keep the pin HIGH during power cycles, assuming the
MCU/MPU pin tristates during the reset condition.The pull-up
resistor value should be chosen to ensure the WE pin tracks V
DD
to a high enough value, so that the current drawn when WE is
LOW is not an issue. A 10-k
resistor draws 330 µA when WE
is LOW and V
DD
= 3.3 V.
Figure 3. Use of Pull-up Resistor on WE
VDD
FM28V100
CE2
CE1
WE
MCU / MPU
OE
A 16-0
DQ 7-0
SRAM Drop-In Replacement
The FM28V100 is designed to be a drop-in replacement for
standard asynchronous SRAMs. The device does not require
chip enable pins to toggle for each new address. Both chip
enable pins may remain active indefinitely while V
DD
is applied.
When both chip enable pins are active, the device automatically
detects address changes and a new access begins. It also allows
page mode operation at speeds up to 33 MHz.
A typical application is shown in
Figure 2.
It shows a pull-up
resistor on CE
1
, which will keep the pin HIGH during power
cycles, assuming the MCU / MPU pin tristates during the reset
condition.The pull-up resistor value should be chosen to ensure
the CE
1
pin tracks V
DD
to a high enough value, so that the
current drawn when CE
1
is LOW is not an issue. Although not
required, it is recommended that CE
2
be tied to V
DD
if the
controller provides an active-low chip enable. A 10-k
resistor
draws 330 µA when CE
1
is LOW and V
DD
= 3.3 V.
Figure 2. Use of Pull-up Resistor on CE
1
VDD
FM28V100
CE2
CE1
WE
MCU / MPU
OE
A 16-0
DQ 7-0
For applications that require the lowest power consumption, the
chip enable signal should be active only during memory
accesses. Due to the external pull-up resistor, some supply
current will be drawn while CE
1
is LOW. When CE
1
is HIGH, the
device draws no more than the maximum standby current I
SB
.
Document Number: 001-86202 Rev. *E
Page 5 of 18
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