3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q64C
GD25Q64C
DATASHEET
1
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q64C
Contents
1.
2.
3.
4.
5.
6.
7.
FEATURES
................................................................................................................................................................ 4
GENERAL DESCRIPTION
...................................................................................................................................... 5
MEMORY ORGANIZATION
.................................................................................................................................... 7
DEVICE OPERATION
.............................................................................................................................................. 8
DATA PROTECTION
................................................................................................................................................ 9
STATUS REGISTER
............................................................................................................................................... 11
COMMANDS DESCRIPTION
............................................................................................................................... 13
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
7.10.
7.11.
7.12.
7.13.
7.14.
7.15.
7.16.
7.17.
7.18.
7.19.
7.20.
7.21.
7.22.
7.23.
7.24.
7.25.
7.26.
7.27.
7.28.
7.29.
7.30.
7.31.
7.32.
W
RITE
E
NABLE
(WREN) (06H) ......................................................................................................................... 16
W
RITE
D
ISABLE
(WRDI) (04H) ......................................................................................................................... 16
W
RITE
E
NABLE FOR
V
OLATILE
S
TATUS
R
EGISTER
(50H) .................................................................................. 17
R
EAD
S
TATUS
R
EGISTER
(RDSR) (05H
OR
35H
OR
15H) .................................................................................. 17
W
RITE
S
TATUS
R
EGISTER
(WRSR) (01H
OR
31H
OR
11H) ................................................................................ 18
R
EAD
D
ATA
B
YTES
(READ) (03H) .................................................................................................................... 19
R
EAD
D
ATA
B
YTES AT
H
IGHER
S
PEED
(F
AST
R
EAD
) (0BH) .............................................................................. 19
D
UAL
O
UTPUT
F
AST
R
EAD
(3BH) ...................................................................................................................... 20
Q
UAD
O
UTPUT
F
AST
R
EAD
(6BH) ..................................................................................................................... 21
D
UAL
I/O F
AST
R
EAD
(BBH) ............................................................................................................................. 22
Q
UAD
I/O F
AST
R
EAD
(EBH) ............................................................................................................................. 23
Q
UAD
I/O W
ORD
F
AST
R
EAD
(E7H) .................................................................................................................. 25
S
ET
B
URST WITH
W
RAP
(77H) ........................................................................................................................... 27
P
AGE
P
ROGRAM
(PP) (02H) ............................................................................................................................... 27
Q
UAD
P
AGE
P
ROGRAM
(32H)............................................................................................................................. 29
F
AST
P
AGE
P
ROGRAM
(FPP) (F2H) .................................................................................................................... 30
S
ECTOR
E
RASE
(SE) (20H) ................................................................................................................................. 31
32KB B
LOCK
E
RASE
(BE) (52H) ....................................................................................................................... 31
64KB B
LOCK
E
RASE
(BE) (D8H) ...................................................................................................................... 32
C
HIP
E
RASE
(CE) (60/C7H) ............................................................................................................................... 32
D
EEP
P
OWER
-D
OWN
(DP) (B9H) ....................................................................................................................... 33
R
ELEASE FROM
D
EEP
P
OWER
-D
OWN OR
H
IGH
P
ERFORMANCE
M
ODE AND
R
EAD
D
EVICE
ID (RDI) (ABH)...... 33
R
EAD
M
ANUFACTURE
ID/ D
EVICE
ID (REMS) (90H)........................................................................................ 34
D
UAL
I/O R
EAD
M
ANUFACTURE
ID/ D
EVICE
ID (92H)...................................................................................... 35
Q
UAD
I/O R
EAD
M
ANUFACTURE
ID/ D
EVICE
ID (94H) ..................................................................................... 36
R
EAD
I
DENTIFICATION
(RDID) (9FH) ................................................................................................................ 37
H
IGH
P
ERFORMANCE
M
ODE
(HPM) (A3H) ........................................................................................................ 38
P
ROGRAM
/E
RASE
S
USPEND
(PES) (75H) ........................................................................................................... 38
P
ROGRAM
/E
RASE
R
ESUME
(PER) (7AH) ........................................................................................................... 39
E
RASE
S
ECURITY
R
EGISTERS
(44H) ................................................................................................................... 39
P
ROGRAM
S
ECURITY
R
EGISTERS
(42H).............................................................................................................. 40
R
EAD
S
ECURITY
R
EGISTERS
(48H)..................................................................................................................... 41
2
3.3V Uniform Sector
Dual and Quad Serial Flash
7.33.
7.34.
8.
GD25Q64C
E
NABLE
R
ESET
(66H)
AND
R
ESET
(99H) ............................................................................................................ 42
R
EAD
S
ERIAL
F
LASH
D
ISCOVERABLE
P
ARAMETER
(5AH) ................................................................................. 42
ELECTRICAL CHARACTERISTICS
................................................................................................................... 47
8.1.
8.2.
8.3.
8.4.
8.5.
8.6.
POWER-ON TIMING ....................................................................................................................................... 47
INITIAL DELIVERY STATE ........................................................................................................................... 47
ABSOLUTE MAXIMUM RATINGS ............................................................................................................... 47
CAPACITANCE MEASUREMENT CONDITIONS ....................................................................................... 48
DC CHARACTERISTICS................................................................................................................................. 49
AC CHARACTERISTICS................................................................................................................................. 50
9.
ORDERING INFORMATION
................................................................................................................................. 53
9.1.
V
ALID
P
ART
N
UMBERS
...................................................................................................................................... 54
PACKAGE INFORMATION
............................................................................................................................... 55
P
ACKAGE
SOP8 208MIL ................................................................................................................................... 55
P
ACKAGE
DIP8 300MIL .................................................................................................................................... 56
P
ACKAGE
WSON 8 (6*5
MM
) ............................................................................................................................. 57
P
ACKAGE
TFBGA-24BALL (6*4
BALL ARRAY
) ................................................................................................ 58
P
ACKAGE
SOP16 300MIL.................................................................................................................................. 59
P
ACKAGE
USON8 (4*4
MM
, 0.45
MM THICKNESS
) .............................................................................................. 60
REVISION HISTORY
.......................................................................................................................................... 61
10.
10.1.
10.2.
10.3.
10.4.
10.5.
10.6.
11.
3
3.3V Uniform Sector
Dual and Quad Serial Flash
1. FEATURES
◆
GD25Q64C
64M-bit Serial Flash
-8192K-byte
-256 bytes per programmable page
◆
Program/Erase Speed
-Page Program time: 0.6ms typical
-Sector Erase time: 50ms typical
-Block Erase time: 0.15/0.20s typical
◆
Standard, Dual, Quad SPI
-Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
-Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#
-Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
◆
-Chip Erase time: 25s typical
Flexible Architecture
-Sector of 4K-byte
-Block of 32/64k-byte
◆
Low Power Consumption
-20mA maximum active current
-5uA maximum power down current
◆
High Speed Clock Frequency
-120MHz for fast read with 30PF load
-Dual I/O Data transfer up to 240Mbits/s
-Quad I/O Data transfer up to 480Mbits/s
-Continuous Read With 8/16/32/64-byte Wrap
◆
Advanced Security Features
(1)
-3*1024-Byte Security Registers With OTP Locks
-Discoverable parameters(SFDP) register
◆
Software/Hardware Write Protection
-Write protect all/portion of memory via software
-Enable/Disable protection with WP# Pin
-Top or Bottom, Sector or Block selection
◆
Single Power Supply Voltage
-Full voltage range:2.7~3.6V
◆
◆
Package Information
-SOP8 (208mil)
-DIP8 (300mil)
Allows XIP(execute in place)operation
(1)
◆
Cycling endurance
-Minimum 100,000 Program/Erase Cycles
-WSON8 (6*5mm)
-TFBGA-24(6*4 ball array)
-SOP16 (300mil)
◆
Data retention
-20-year data retention typical
-USON8 (4*4mm)
Note: 1.Please contact GigaDevice for details.
4
3.3V Uniform Sector
Dual and Quad Serial Flash
2. GENERAL DESCRIPTION
GD25Q64C
The GD25Q64C (64M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O
data is transferred with speed of 240Mbits/s and the Quad I/O & Quad output data is transferred with speed of 480Mbits/s.
Connection Diagram
CS#
SO
WP#
VSS
1
2
Top View
3
4
6
5
8–LEAD SOP/DIP
SCLK
SI
WP# 3
VSS 4
8–LEAD WSON/USON
8
7
VCC
HOLD#
CS#
SO
1
2
Top View
6 SCLK
5
SI
8
7
VCC
HOLD#
Top View
4
NC
3
NC
2
NC
1
NC
NC
NC
NC
NC
NC
SCLK CS#
SO
NC
NC
VSS
NC
SI
NC
NC
VCC
WP# HOLD# NC
NC
HOLD#
VCC
NC
NC
NC
NC
CS#
SO
1
2
3
4
Top View
5
6
7
8
16-LEAD SOP
16
15
14
13
12
11
10
9
SCLK
SI
NC
NC
NC
NC
VSS
WP#
A
B
C
D
E
F
24-BALL TFBGA
Pin Description
Pin Name
CS#
SO (IO1)
WP# (IO2)
VSS
SI (IO0)
SCLK
HOLD# (IO3)
VCC
I/O
I
I/O
I/O
I
I/O
I/O
Description
Chip Select Input
Data Output (Data Input Output 1)
Write Protect Input (Data Input Output 2)
Ground
Data Input (Data Input Output 0)
Serial Clock Input
Hold Input (Data Input Output 3)
Power Supply
Note: CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on.
5