Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute
maximum ratings for extended periods may affect device reliability. Operating ranges define those limits between which the functionality of the device is guaranteed.
Electrical Characteristics
VCC = 2.5 to 5.5V, T
A
= Operating Temperature Range, unless otherwise noted.
Parameter
Operating Voltage Range, VCC
Supply Current, ICC
Reset Voltage Threshold, VTH
Reset Timeout Period
VCC = 5.5V, no load
VCC = 3.6V, no load
Note 1
V
TH
- 2.5%
20
140
1100
VCC > 4.25V, ISink = 3.2mA
VCC > 2.5V, ISink = 1.2mA
VCC > 1.4V, ISink = 50µA
RESET deasserted
10
0.5
VTH > 4.0V
VTH < 4.0V
VTH > 4.0V
VTH < 4.0V
10
20
100
2.3
0.7 X VCC
0.8
0.25 X VCC
30
Conditions
Min
1.4
9
6
V
TH
28
200
1500
Typ
Max
5.5
15
10
V
TH
+ 2.5%
44
320
2500
0.4
0.3
0.3
1
Units
V
µA
V
ms
ms
ms
V
RESET Output Voltage, VOL
RESET Output Leakage
MR Minimum Pulse Width
MR to Reset Delay
MR Input Threshold, VIH
MR Input Threshold, VIL
MR Pull-Up Resistance
MR Glitch Immunity
µA
µs
µs
V
V
V
V
kΩ
ns
Note 1:
Various reset threshold option available. See Ordering Information on page 7 for details.
2
MIC6315 Open-Drain
µP
Reset Circuit
Pin Functions
Pin No.
GND
RESET
MR
Pin Name
1
2
3
Description
IC Ground Pin.
RESET goes low if VCC falls below the reset threshold and remains asserted for one
reset timeout period after VCC exceeds the reset threshold.
Manual reset input. A logic low on MR forces a reset. The reset will remain asserted
as long as MR is held low and for one reset timeout period after MR goes high. This
input can be shorted to ground via a switch or driven from CMOS or TTL logic. Float if
unused.
Power supply input, 3V, 3.3V or 5V.
VCC
4
3
MIC6315 Open-Drain
µP
Reset Circuit
Block Diagram
VCC (4)
Reset
Threshold (V)
+
-
RESET
GENERATOR
RESET (2)
MR (3)
GND (1)
Figure 1. MIC6315 Block Diagram
4
MIC6315 Open-Drain
µP
Reset Circuit
Circuit Description
Microprocessor Reset
The RESET pin is asserted whenever VCC falls below
the reset threshold voltage or if MR (manual reset) is
forced low. The RESET pin remains asserted for the
duration of the reset timeout period after VCC has risen
above the reset threshold voltage or MR has returned
high. The reset function ensures the microprocessor is
properly reset and powers up into a known condition
after a power failure. RESET will remain valid with VCC
as low as 1.4V.
The RESET output is a simple open-drain N-channel
MOSFET structure. A pull-up resistor must be used to
pull this output up to some voltage. For most applica-
tions, this voltage will be the same power supply that
supplies VCC to the MIC6315. It is possible however to
tie this resistor to some other voltage. This will allow the
MIC6315 to monitor one voltage while level-shifting the
RESET output to some other voltage. The pullup voltage
must be limited to 6.0V or less to avoid damage to the
MIC6315. The resistor must be small enough to supply
VCC
Vthr
MR
t1
RESET
t1
Figure 2. Reset Timing Diagram
current to the inputs and leakage paths that are driven by
the RESET output.
As VCC drops to 0V, the MIC6315 will no longer be able
to pull the RESET output low. At this point, the pullup
resistor will pull the output high. The value of the pullup
resistor and the voltage it is connected to will affect the
point at which this happens.
Because the RESET output is open-drain, several reset
sources can be wire-ORed in parallel to allow resets
from multiple sources.
VCC Transients
The MIC6315 is relatively immune to negative-going
VCC glitches below the reset threshold. Typically, a
negative-going transient 125mV below the reset
threshold with a duration of 25µs or less will not cause
an unwanted reset. If additional transient immunity is
needed, a bypass capacitor can be placed as close as
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