PTN3700
1.8 V simple mobile interface link bridge IC
Rev. 01 — 14 August 2007
Product data sheet
1. General description
The PTN3700 is a 1.8 V simple mobile interface link bridge IC which can function both as
a transmitter-serializer or a receiver-deserializer for RGB888 video data. When configured
as transmitter (using input pin TX/RX), the PTN3700 serializes parallel CMOS video input
data into 1, 2 or 3 subLVDS-based high-speed serial data channels. When configured as
receiver, the PTN3700 deserializes up to 3 high-speed serial data channels into parallel
CMOS video data signals.
The parallel interface of the PTN3700 is based on the conventional and widely used 24-bit
wide data bus for RGB video data, plus active LOW HS (Horizontal Synchronization) and
VS (Vertical Synchronization) signals, and an active HIGH DE (Data Enable) signal. An
additional two auxiliary bits A[1:0] are provided to permit signaling of miscellaneous status
or mode information across the link to the display. The serial interface link of the PTN3700
is based on the open Simple Mobile Interface Link (SMILi) definition. In order to keep
power low while accommodating various display sizes (e.g., up to 24-bit, 60 frames per
second XVGA), the number of high-speed serial channels (‘lanes’) is configurable from
1 to 3 depending on the bandwidth needed. The data link speed is determined by the
PCLK (Pixel Clock) rate and the number of serial channels selected.
In order to maintain a low power profile, the PTN3700 has three power modes,
determined by detection of an active input clock and by shutdown pin XSD. In Shutdown
mode (XSD = LOW), the PTN3700 is completely inactive and consumes a minimum of
current. In Standby mode (XSD = HIGH), the device is ready to switch to Active mode as
soon as an active input clock signal is detected, and assume normal link operation.
In Transmitter mode, the PTN3700 performs parity calculation on the input data (R[7:0],
G[7:0], B[7:0] plus HS, VS and DE data bits) and adds an odd parity bit CP to the serial
transmitted data stream. The PTN3700 in Receiver mode also integrates a parity
checking function, which checks for odd parity across the decoded input word (R[7:0],
G[7:0], B[7:0] plus HS, VS and DE data bits), and indicates whether a parity error has
occurred on its CPO out pin (active HIGH). When a parity error occurs, the most recent
error-free pixel data will be output instead of the received invalid pixel data.
PTN3700 in Receiver mode offers an optional advanced frame mixing feature, which
allows 18-bit displays to effectively display 24-bit color resolution by applying a
patent-pending pixel data processing algorithm to the 24-bit video input data.
One of two serial transmission methods is selectable: pseudo source synchronous
transmission based on the pixel clock, or true source synchronous transmission based on
the bit clock. The latter uses a patent-pending methodology characterized by zero
overhead and operation guaranteed free from false pixel synchronization.
NXP Semiconductors
PTN3700
1.8 V simple mobile interface link bridge IC
The PTN3700 automatically rotates the order of the essential signals (parallel CMOS and
high-speed serial data and clock) depending on whether it is operating as transmitter or as
receiver (using pin TX/RX). In addition, two Pinning Select bits (inputs PSEL[1:0]) allow for
four additional signal order configurations. This allows for various topologies of printed
circuit board or flex foil layout without crossing of traces; and enables the easy introduction
of PTN3700 into an existing ‘parallel’ design avoiding board re-layout.
The PTN3700 is available in a 56-ball VFBGA package and operates across a
temperature range of
−40 °C
to +85
°C.
2. Features
I
Configurable as either Transmitter or Receiver
I
One of two serial transmission methods selectable (pixel clock referenced pseudo
source synchronous or bit clock referenced true source synchronous)
I
3 differential subLVDS high-speed serial lanes
I
One differential pixel clock
I
Configurable aggregate data bandwidth allowing up to 24-bit color, 60 fps XGA:
N
1 lane at 30× serialization rate up to 650 Mbit/s
N
2 lanes at 15× serialization rate up to 1300 Mbit/s
N
3 lanes at 10× serialization rate up to 1.95 Gbit/s
I
Parity encoding (transmitter) and detection (receiver) with last valid pixel repetition
I
Advanced Frame Mixing function (in Receiver mode) for 24-bit color depth using
conventional 18-bit displays or specially adapted ‘18-bit plus’ displays
I
Parallel CMOS I/O based on interface definition of RGB888 plus HS, VS, DE
I
Very low power profile:
N
Shutdown mode for minimum idle power (< 3
µA
typical)
N
Low-power Standby mode with input clock frequency auto-detect (< 3
µA
typical)
N
Low active transmitter power: 18 mW (typ.) for QVGA
1
and 40 mW (typ.) for
WVGA
2
N
Low active receiver power: 15 mW (typ.) for QVGA and 36 mW (typ.) for WVGA
I
Slew rate control on receiver parallel CMOS outputs
I
Operates from a single 1.8 V
±
150 mV power supply
I
Configurable mirroring pinout (dependent on Tx or Rx mode and PSEL[1:0] inputs) for
optimum single layer flex-foil flow-through in various application scenarios
I
Available in 56-ball VFBGA package
3. Applications
I
High-resolution mobile phones
I
Portable applications with video display capability
1.
2.
QVGA: 240
×
320 pixels at 60 Hz frame rate; 20 % non-active display data overhead; PCLK at 5.5 MHz; one-lane operation at
166 Mbit/s; 24-bit color data.
WVGA: 854
×
480 pixels at 60 Hz frame rate; 20 % non-active display data overhead; PCLK at 29.5 MHz; two-lane operation at
885.4 Mbit/s; 24-bit color data.
© NXP B.V. 2007. All rights reserved.
PTN3700_1
Product data sheet
Rev. 01 — 14 August 2007
2 of 41
NXP Semiconductors
PTN3700
1.8 V simple mobile interface link bridge IC
4. Ordering information
Table 1.
Ordering information
Solder process
Package
Name
PTN3700EV/G
Description
Version
SOT991-1
Type number
Pb-free (SnAgCu
VFBGA56 plastic very thin fine-pitch ball grid array package;
solder ball compound)
56 balls; body 4
×
4.5
×
0.65 mm
[1]
[1]
0.5 mm ball pitch; 1.0 mm maximum package height.
4.1 Ordering options
Table 2.
Ordering options
Topside mark
3700
Temperature range
−40 °C
to +85
°C
Type number
PTN3700EV/G
5. Functional diagram
VDD
VDDA
PTN3700
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
A[1:0]
2
8
8
8
D0+
D0−
PROTOCOL MAPPING,
PARITY ENCODING,
SYNC WORD ENCODING
INPUT
REGISTER
SERIALIZER
D1+
D1−
D2+
D2−
N
×
PCLK
PCLK
PLL
1
×
PCLK
÷
2
1
0
FSS
CLK+
CLK−
FSS
XSD
LS[1:0]
PSEL[1:0]
2
2
CONFIGURATION
AND
POWER MANAGEMENT
TX/RX = HIGH
GND
GNDA
002aab363
Fig 1. Functional diagram of PTN3700 in Transmitter mode
PTN3700_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 14 August 2007
3 of 41
NXP Semiconductors
PTN3700
1.8 V simple mobile interface link bridge IC
VDD
VDDA
PTN3700
D0+
8
8
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
D0−
D1+
DESERIALIZER
D1−
D2+
2
PROTOCOL PARSING,
PARITY DETECTION,
ADVANCED
FRAME MIXING,
SYNC WORD DECODING
8
OUTPUT
REGISTER
A[1:0]
D2−
N
×
PCLK
0
PLL
PCLK
1
DDR
→
SDR
FSS
CPO
CLK+
CLK−
FM
FSS
F/XS
XSD
LS[1:0]
PSEL[1:0]
2
2
CONFIGURATION
AND
POWER MANAGEMENT
TX/RX = LOW
GND
GNDA
002aab364
Fig 2. Functional diagram of PTN3700 in Receiver mode
PTN3700_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 14 August 2007
4 of 41
NXP Semiconductors
PTN3700
1.8 V simple mobile interface link bridge IC
6. Pinning information
6.1 Pinning
ball A1
index area
PTN3700EV/G
1 2 3 4 5 6 7
A
B
C
D
E
F
G
H
002aac377
Transparent top view
Fig 3. Ball configuration for VFBGA56
1
A
B
C
D
E
F
G
H
D2+
D2−
D1+
D1−
CLK+
CLK−
D0+
D0−
2
VDDA
GNDA
TX/RX
VDD
GND
F/XS
XSD
CPO
3
DE
VS
A1
PSEL0
PSEL1
A0
R6
R7
4
HS
PCLK
GND
LS0
LS1
GND
R4
R5
5
B0
B1
VDD
FM
FSS
VDD
R2
R3
6
B2
B3
B6
G0
G2
G4
R0
R1
7
B4
B5
B7
G1
G3
G5
G6
G7
002aac378
1
A
B
C
D
E
F
G
H
D2+
D2−
D1+
D1−
CLK+
CLK−
D0+
D0−
2
VDDA
GNDA
TX/RX
VDD
GND
F/XS
XSD
CPO
3
DE
VS
A1
PSEL0
PSEL1
A0
B1
B0
4
HS
PCLK
GND
LS0
LS1
GND
B3
B2
5
R7
R6
VDD
FM
FSS
VDD
B5
B4
6
R5
R4
R1
G7
G5
G3
B7
B6
7
R3
R2
R0
G6
G4
G2
G1
G0
002aac379
56-ball, 7
×
8 grid; transparent top view
56-ball, 7
×
8 grid; transparent top view
Fig 4. VFBGA56 ball mapping - Transmitter mode
(TX/RX = HIGH); PSEL[1:0] = 00b
1
A
B
C
D
E
F
G
H
D0−
D0+
CLK−
CLK+
D1−
D1+
D2−
D2+
2
VDDA
GNDA
TX/RX
VDD
GND
F/XS
XSD
CPO
3
DE
VS
A1
PSEL0
PSEL1
A0
R6
R7
4
HS
PCLK
GND
LS0
LS1
GND
R4
R5
5
B0
B1
VDD
FM
FSS
VDD
R2
R3
6
B2
B3
B6
G0
G2
G4
R0
R1
7
B4
B5
B7
G1
G3
G5
G6
G7
002aac380
Fig 5. VFBGA56 ball mapping - Transmitter mode
(TX/RX = HIGH); PSEL[1:0] = 01b
1
A
B
C
D
E
F
G
H
D0−
D0+
CLK−
CLK+
D1−
D1+
D2−
D2+
2
VDDA
GNDA
TX/RX
VDD
GND
F/XS
XSD
CPO
3
DE
VS
A1
PSEL0
PSEL1
A0
B1
B0
4
HS
PCLK
GND
LS0
LS1
GND
B3
B2
5
R7
R6
VDD
FM
FSS
VDD
B5
B4
6
R5
R4
R1
G7
G5
G3
B7
B6
7
R3
R2
R0
G6
G4
G2
G1
G0
002aac381
56-ball, 7
×
8 grid; transparent top view
56-ball, 7
×
8 grid; transparent top view
Fig 6. VFBGA56 ball mapping - Transmitter mode
(TX/RX = HIGH); PSEL[1:0] = 10b
PTN3700_1
Fig 7. VFBGA56 ball mapping - Transmitter mode
(TX/RX = HIGH); PSEL[1:0] = 11b
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 14 August 2007
5 of 41
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
