PRELIMINARY
‡
256Mb MULTIBANK BURST FLASH
32Mb/64Mb BURST CellularRAM COMBO
FLASH AND CellularRAM
™
COMBO MEMORY
Features
Stacked die Combo package
• Includes two 128Mb Flash devices
• Choice of either one 32Mb or one 64Mb
CellularRAM device
Basic configuration
Flash
• Flexible multibank architecture
• 8 Meg x 16 Async/Page/Burst interface
• Support for true concurrent operations with no
latency
CellularRAM
• Low power, high-density design
• 2 Meg x 16 or 4 Meg x 16 configurations
• Burst
F_V
CC
, V
CC
Q, F_V
PP
, C_V
CC
voltages
• 1.70V (MIN)/1.95V (MAX) F_V
CC
, C_V
CC
• 1.70V (MIN)/2.24V (MAX) V
CC
Q
• 1.80V (TYP) F_V
PP
(in-system PROGRAM/ERASE)
• 12V ±5% (HV) F_V
PP
tolerant (factory program-
ming compatibility)
Fast programming Algorithm (FPA)
Enhanced suspend options
• ERASE-SUSPEND-to-READ within same bank
• PROGRAM-SUSPEND-to-READ within same
bank
• ERASE-SUSPEND-to-PROGRAM within same
bank
Each Flash contains two 64-bit chip protection
registers for security purposes
100,000 ERASE cycles per block
Cross-compatible command set support
• Extended command set
• Common Flash interface (CFI) compliant
MT28C256532W18T
MT28C256564W18T
Low Voltage, Wireless Temperature
Figure 1: 88-Ball FBGA
1
A
B
C
D
E
F
G
H
J
K
L
M
NC
2
NC
3
4
5
6
7
NC
8
NC
A4
A18
A19
C_V
SS
F_V
CC
F_V
CC
A21
A11
A5
C_LB#
A23
C_V
SS
NC
CLK
A22
A12
A3
A17
RFU
F_V
PP
C_WE#
C_CE#
A9
A13
A2
A7
RFU
F_WP#
ADV#
A20
A10
A15
A1
A6
C_UB#
F_RST#
F_WE#
A8
A14
A16
A0
DQ8
DQ2
DQ10
DQ5
DQ13
WAIT#
NC
C_OE#
DQ0
DQ1
DQ3
DQ12
DQ14
DQ7
NC
NC
F_OE#
DQ9
DQ11
DQ4
DQ6
DQ15
V
CC
Q
F_CE#
NC
NC
NC
C_V
CC
F_V
CC
V
CC
Q
C_CRE
C_V
SS
V
SS
Q
VCCQ
F_VCC
C_V
SS
V
SS
Q
F_V
SS
C_V
SS
NC
NC
NC
NC
Top View
(Ball Down)
Flash Boot Block Configuration
• Top/Top
• Top/Bottom
• Bottom/Top
• Bottom/Bottom
CellularRAM Timing
• 70ns
• 85ns
CellularRAM Burst Frequency
• 66 MHz
Options
Flash Timing
• 60ns
1
• 70ns
Flash Burst Frequency
• 66 MHz
1
• 54 MHz
I/O Voltage Range
• V
CC
Q 1.70V–2.24V
Operating Temperature Range
• Wireless Temperature (-25°C to +85°C)
Package
• 88-ball FBGA (Standard) 8 x 10 grid with eight
support balls
• 88-ball FBGA (Lead-free) 8 x 10 grid with eight
support balls
2
NOTE:
1. Contact factory for availability.
2. Contact factory for details.
09005aef80c7d5a5
MT28C256564W18T.fm - Rev. C Pub 2/04 EN
1
©2004 Micron Technology, Inc. All rights reserved.
‡
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
PRELIMINARY
256Mb MULTIBANK BURST FLASH
32Mb/64Mb BURST CellularRAM COMBO
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Flash Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
MultiChip Packaging Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Unique IDs, State Machines, and Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Flash Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Flash Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Data Sheet Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
09005aef80c7d5a5
MT28C256564W18T.fm - Rev. C Pub 2/04 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc. All rights reserved.
PRELIMINARY
256Mb MULTIBANK BURST FLASH
32Mb/64Mb BURST CellularRAM COMBO
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
88-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
88-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
09005aef80c7d5a5
MT28C256564W18T.fm - Rev. C Pub 2/04 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc. All rights reserved.
PRELIMINARY
256Mb MULTIBANK BURST FLASH
32Mb/64Mb BURST CellularRAM COMBO
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Cross-Reference for Abbreviated Device Marks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Valid Part Number Combinations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Truth Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
CFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
09005aef80c7d5a5
MT28C256564W18T.fm - Rev. C Pub 2/04 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc. All rights reserved.
PRELIMINARY
256Mb MULTIBANK BURST FLASH
32Mb/64Mb BURST CellularRAM COMBO
Device General Description
The MT28C256532W18T/MT28C256564W18T com-
bination Flash and CellularRAM is a high-perfor-
mance, high-density, memory solution that can
significantly improve system performance. This mem-
ory solution is comprised of two 128Mb Flash devices
and one 32Mb or one 64Mb CellularRAM device.
It is important to note that the specifications con-
tained in this document supersede the specifications
listed in the referenced individual Flash and Cellular-
RAM data sheets.
words each (524,288 bits). The parameter blocks are
addressed either by the low order addresses (bottom
boot) or by the higher order addresses (top boot).
The two Flash devices can be supplied with any
combination of top or bottom boot (e.g., top/top, bot-
tom/bottom, top/bottom, or bottom/top). Please see
Figures 1 and 2 for more information.
CellularRAM General Description
The CellularRAM architecture features high-speed
CMOS, dynamic random-access memories developed
for low-power portable applications The CellularRAM
device is available in either 32Mb or 64Mb densities.
To operate seamlessly on a burst Flash bus,
CellularRAM
products
have
incorporated
a
transparent self-refresh mechanism. The hidden
refresh requires no additional support from the system
memory controller and has no significant impact on
device read/write performance.
The refresh configuration register (RCR) is used to
control how refresh is performed on the CellularRAM
array. These registers are automatically loaded with
default settings during power-up and can be updated
any time during normal operation. Special attention
has been focused on standby current consumption
during self-refresh.
CellularRAM products include three system-acces-
sible mechanisms used to minimize standby current.
Partial array refresh (PAR) limits refresh to the portion
of the memory array being used. Temperature com-
pensated refresh (TCR) is used to adjust the refresh
rate according to the ambient temperature. The
refresh rate can be decreased at lower temperatures to
minimize current consumption during standby. Deep
sleep mode halts the refresh operation altogether and
is used when no vital information is stored in the
device. These three refresh mechanisms are adjusted
through the refresh configuration register (RCR).
For
device
specifications
and
additional
documentation concerning CellularRAM memory, please
refer
to
the
MT45W2MW16BFB
and
MT45W4MW16BFB CellularRAM data sheets at
www.micron.com/cellularram.
Flash General Description
The Flash architecture features a multipartition
configuration that supports READ-While-PROGRAM/
ERASE operations with no latency. An 8Mb partition
size enables optimal design flexibility.
Two Flash devices are stacked to achieve the 256Mb
density. Both Flash die share a dedicated CE# and OE#
control.
The stacked Flash device enables soft protection for
blocks, as read only, by configuring soft protection reg-
isters with dedicated command sequences. For secu-
rity purposes, two user-programmable 64-bit chip
protection registers are provided for each Flash device.
The embedded WORD PROGRAM and BLOCK
ERASE functions are fully automated by an on-chip
write state machine (WSM). An on-chip device status
register can be used to monitor the WSM status and
determine the progress of the PROGRAM/ERASE tasks.
Each Flash device has a read configuration register
(RCR) that defines how the Flash interacts with the
memory bus. For device specifications and additional
documentation concerning Flash, please refer to the
MT28F1284W18 data sheet at
www.micron.com/flash.
Flash Configurations
Each Flash memory implements a multibank archi-
tecture (16 banks of 8Mb each) to allow concurrent
operations. Any address within a block address range
selects that block for the required READ, PROGRAM, or
ERASE operation.
Each Flash memory features eight 8K-word sectors
(8 x 65,536 bits), designated as parameter blocks, and
the remaining part is organized in main blocks of 64K
09005aef80c7d5a5
MT28C256564W18T.fm - Rev. C Pub 2/04 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc. All rights reserved.
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