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2.5 Gbit/s
Clock and Data
Recovery
GD16522
General Description
The GD16522 is a high performance
monolithic integrated multi-rate
Clock
and Data Recovery
(CDR) device appli-
cable for optical communication systems
including:
u
SDH STM-16 / 4 / 1
u
SONET OC-48 / 12 / 3
u
Gigabit Ethernet
The GD16522 features:
u
Limiting input amplifier.
u
Analogue peak level detection circuit.
u
Digital Loss Of Signal (LOS) monitor
circuit with four selectable threshold
settings.
u
Consecutive Identical Binary Digit
alarm output.
The device also features an additional
high-speed data input for serial loop-back
diagnostic tests.
The CDR contains all circuits needed for
reliable acquisition and lock of the VCO
phase to the incoming data-stream.
The electrical input sensitivity is better
than 8 mV (BER <10
-10
).
The device exceeds all ITU-T and
Bellcore IEEE jitter requirements when
used with the recommended loop filter
(jitter tolerance, -transfer and -genera-
tion).
The output clock (2.488 GHz when
STM-16 data input is selected) is main-
tained within 500 ppm tolerance of the
reference frequency in the absence of
data.
The GD16522 is available in 48 lead
7 × 7 mm TQFP power enhanced plastic
package.
VCTL
BRS0
BRS1
SELTCK
VCC
VCCL
VCCO
VCCP
VCCV
Features
l
Exceeds ITU-T and Bellcore require-
ments of Jitter Transfer, Generation
and Tolerance.
Integrated Limiting Amplifier.
Digital LOS monitor and alarm output.
Bit Consecutive Detect Output.
Multi-rate data input.
Differential CML data input with inter-
nal 50
W
load termination.
Control inputs are LVTTL.
Reference clock selectable:
– 155.52 MHz
– 38.88 MHz
Single supply operation: +3.3 V.
High-speed serial loop-back input.
Output signal shutdown input.
Available in 48 pin TQFP package
(7 × 7 mm).
l
l
l
l
l
l
l
l
l
DEC_ADJ SD_SEL
TCK
l
l
MON
MON_REF
SDIP
DIREF
SDIN
DIREFN
Peak
Detect
VCO
Divider
MUX
Limiting
Amplifier
B.B
Phase
Detector
SCOP
SCON
SDOP
SDON
Applications
l
SDOWN_G
SDOWN_L
SLBIP
SLBIN
SBER0
SBER1
1/4
Amplifier
BEF
Lock
Detect
Continuous
Bit
Detector
Clock and Data Recovery for optical
communication systems including:
– SDH STM-16 / 4 / 1
– SONET OC-48 / 12 / 3
– Gigabit Ethernet
BC_DET
LOCK_DET
LOS_DET
RCIP
RCIN
MUX
Phase
Frequency
Detect
MUX
PCTL
VEE
VEEL
VEEP
VEEV
REF_SEL
CDR_SEL
Data Sheet Rev.: 21
Functional Details
The main application of the GD16522 is
as a receiver for optical communication
systems:
u
SDH STM-16 / 4 / 1
u
SONET OC-48 / 12 / 3
u
Gigabit Ethernet
The GD16522 integrates:
u
a Limiting Amplifier
u
a Digital LOS Alarm
u
a Continuous Bit Detector
u
Serial loop-back input
u
a Voltage Controlled Oscillator (VCO)
u
a Lock Detect Circuit
u
a Frequency Detector (PFD)
u
a Bang-Bang Phase Detector
into a
Phase Locked Loop
(PLL) - based
multi-rate clock and data recovery circuit
with differential CML data and clock
outputs.
using REF_SEL pin the reference clock
input (RCIP/N) can be chosen to use a
155.52 MHz or 38.88 MHz differential
PECL reference clock. The reference
clock frequency is independent of the
chosen data rate.
The LOCK_DET Signal
The LOCK_DET signal is a status output,
which monitors the status of the internal
lock detect circuit of the GD16522 CDR
logic and the output of the BC_DET cir-
cuit.
LOCK_DET is asserted (set HIGH) if the
VCO frequency differs from the reference
frequency by
±500
ppm. This ‘ out of
lock’ condition is detected by the internal
Lock Detect circuit described previously.
LOCK_DET is also asserted in the case
of the absence of data, which is detected
by the BC_DET circuit within the reaction
time of the internal PLL lock detect
system.
If data is absent, the divided VCO fre-
quency will drift away from the reference
frequency until they differ by
±500
ppm.
The internal Lock Detect logic will alter-
nate between CDR and acquisition mode
until data returns, enabling the GD16522
to acquire lock and function in CDR
mode.
The LOCK_DET signal, however, will re-
main asserted until BC_DET is de- as-
serted and the internal lock detect circuit
is operating in CDR mode.
The CDR circuitry of the GD16522 has
been fine-tuned to provide an accurate
stable clock output from the VCO when
data is present. Due to the precise nature
of the internal VCO, when data is absent
the clock output frequency will drift slowly
from the recovered clock frequency until
an out of lock condition is detected. The
time taken for the GD16522 to go ‘out of
lock’ in the absence of data will typically
be at least 3 ms, unless an external cir-
cuit is used to pull the VCO frequency
away from the reference frequency.
When loss of data is detected, i.e.
BC_DET is asserted, or the divided VCO
frequency differs from the reference fre-
quency by
±500
ppm, LOCK_DET is as-
serted and the internal lock detect circuit
switches to acquisition mode. This will
give a stable output clock during a loss of
data condition.
When BC_DET is de-asserted and the
divided VCO frequency is within 500 ppm
of the reference frequency, LOCK_DET
will be de-asserted within 500
ms,
inde-
pendent of selected data rate.
A bonding option is available which en-
ables the LOCK_DET output to monitor
the status of the LOS_DET circuit in ad-
dition to the internal lock and BC_DET.
The BC_DET Signal
An internal circuit monitors input data
transitions and gives a BC_DET output
signal which is asserted if more than 256
consecutive identical bits, 0s or 1s, are
detected.
BC_DET will be de-asserted only after
approximately 16 bit transitions are de-
tected within a time period proportional to
the selected data rate (50 ns at STM 16 /
OC-48).
VCO
The VCO is a low noise LC-type differen-
tial oscillator with a tuning range from 2.4
to 2.6 GHz. Tuning is done by applying a
voltage to the VCTL pin.
Bang-Bang Phase Detector
The Bang-Bang phase detector is used
in
CDR mode
as a true digital type de-
tector, producing a binary output. It sam-
ples the incoming data twice each bit
period: once in the transition of the (pre-
vious) bit period and once in the middle
of the bit period. When a transition oc-
curs between 2 consecutive bits - the
value of the sample in the transition be-
tween the bits will show whether the
VCO clock leads or lags the data. Hence
the PLL is controlled by the bit transition
point, thereby ensuring that data is sam-
pled in the middle of the eye, once the
system is in CDR mode. The external
loop filter components control the charac-
teristics of the PLL.
The binary output of either the PFD or
the Bang-Bang phase detector (depend-
ing of the mode of the lock-detection cir-
cuit) is passed to a charge pump which
can sink or source current or tristate. The
output of the charge pump is filtered by
the external loop filter and controls the
tuning voltage of the VCO.
As a result of the continuous monitoring
of the lock-detect circuit, the VCO fre-
quency never deviates more than
500 ppm from the reference clock before
the PLL is considered to be ’Out of Lock’.
Hence the acquisition time is predictable
and short and the output clock (SCOP/N)
is always kept within the 500 ppm limits,
ensuring safe clocking of downstream
circuitry.
Lock Detect Circuit
The internal lock detect circuit continu-
ously monitors the difference between
the reference clock and the divided VCO
clock. If the reference clock and the di-
vided VCO frequency differ by more than
500 ppm, it switches the PFD into the
PLL in order to pull the VCO back inside
the lock-in range. This mode is called
the
acquisition mode.
The PFD is used to ensure predictable
lock up conditions for the GD16522 by
locking the VCO to an external reference
clock source. It is only used during acqui-
sition and pulls the VCO into the lock-in
range where the Bang-Bang phase de-
tector is capable of acquiring lock. The
PFD is made with digital set/reset cells
giving it a true phase and frequency
characteristic.
Once the VCO is inside the lock-range
the lock-detection circuit switches the
Bang-Bang phase detector into the PLL
in order to lock to the data signal. This
mode is called
CDR mode.
If the divided VCO frequency differs from
the reference frequency by
±500
ppm,
i.e. due to data loss, the internal lock de-
tect circuit will give a stable output clock
during a loss of data condition.
The reference clock to the PFD is at 1/64
of the STM16 / OC-48 data rate. By
Data Sheet Rev.: 21
GD16522
Page 2 of 12
LOS_DET
The Loss Of Signal DETection
(LOS_DET) alarm output is low during
normal operation.
The LOS_DET signal is the output from a
digital Bit Error Flag (BEF) circuit which
monitors the number of false bit transi-
tions in the data signal. A internal flag is
raised if the number of false transitions is
above a predefined level, i.e. if the Bit
Error Rate (BER) is above a predefined
level.
This has been realised with a counter
counting the false bit transitions. If this
counter runs out within a time period the
BEF flag is set. The length of the counter
may be set by external select signals
(SBER0 and SBER1). The time period
that the false errors are counted within is
64kbits corresponding to 26
ms
at
STM 16 / OC-48 data rate. The length of
the counter may be set to detect bit error
rates of 0.5E-3, 1E-3, 2E-3 or 4E-3.
The input to the BEF circuit is derived
from Bang-Bang detector sample data.
As discussed above, the Bang-Bang de-
tector samples the incoming data twice
each bit period, once at the transition and
once in the middle of the eye. If the value
of the samples in the middle of the eye
for two consecutive bits is equal but the
value of the transition sample is different
then a bit error has occurred.
As the BEF system detects false bit tran-
sitions between two consecutive bits,
only bit errors due to high frequency
noise are detected. Therefore there will
not be a 1:1 correlation between the ac-
tual BER of the signal and the number of
errors detected by the BEF system. The
actual bit error rate is however correlated
to the number of errors detected in the
BEF system. This means that by choos-
ing the appropriate counter length, it will
be possible for the BEF system to set the
BEF flag at a user selectable bit error
rate.
Once the LOS_DET signal has been as-
serted, it will be de-asserted only when
the BER is less than ¼ of the set rate for
a period which is proportional to the se-
lected data rate. (at least 125
ms
at
STM16 / OC-48).
Output Disable
It is possible to set the data (SDOP/N)
outputs of the GD16522 to a defined
logic level by using the shutdown input
pins (SDOWN_L and SDOWN_G).
If both shutdown pins are connected to
VEE they have no effect on the data out-
puts.
By setting SDOWN_L to VCC the data
outputs will be latched to give a fixed
logic 1 output if LOCK_DET is asserted.
By setting SDOWN_G to VCC the data
outputs will be latched to give a fixed
logic 1 output regardless of the state of
LOCK_DET and of the setting of
SDOWN_L.
The Shutdown pins have no effect on the
clock (SCOP/N) outputs.
data. An output voltage is available at the
MON pin, which is proportional to the
peak level of the input signal. MON_REF
is an internally generated fixed reference
voltage. The difference between the
value obtained at the MON pin and the
value of MON_REF indicates the peak
input data signal level.
Application data pertaining to use of
MON, MON_REF and DEC_ADJ is avail-
able from GIGAs Application Depart-
ment.
Outputs
Following the CDR block the re-timed
data is output together with the re-
covered clock. The data and clock out-
puts are differential CML with on-chip
50
W
back termination. The output clock
frequency is related to the selected data
input rate and data output rate (i.e.
2.488 GHz when 2.488 Gbit/s selected;
1.244 GHz when 1.244 Gbit/s selected;
622 MHz when 622 Gbit/s selected;
155 MHz when 155 Gbit/s selected). The
outputs can externally be either AC- or
DC- coupled.
Data Inputs
Limiting Amplifier
The limiting input amplifier is a high per-
formance input data signal conditioning
buffer with sensitivity better than 8 mV.
Data input is CML.
The inputs may be either AC or DC cou-
pled. In both cases input termination is
made through pins DIREF / DIREFN. If
the inputs are AC coupled the amplifier
features an internal offset cancelling DC
feedback. Notice that the offset cancella-
tion will only work when the input is
AC-coupled as shown in the
Figures on
page 4.
The limiting amplifier inputs are opera-
tional when the SD_SEL input is con-
nected to a logic high (VCC).
Alternatively, the high-speed serial loop-
back input can be selected by connecting
SD_SEL to a logic low (VEE) to allow
loop-back diagnostic testing of the
system.
DEC_ADJ
The DEC_ADJ input can be used to com-
pensate for input data with a non-sym-
metric duty cycle, allowing control over
the DC bias level of the limiting amplifier
output. The DC bias point can be steered
up or down by an external potentiometer.
By this means the optimum data sam-
pling point of the Bang-Bang phase de-
tector can be achieved for duty cycles of
30% to 70%. If the DEC_ADJ pin is un-
connected the DC bias will default to an
internally set level optimised for input
data with a 50% duty cycle.
Peak Level Monitor
(MON and MON_REF)
The MON and MON_REF pins can be
used to indicate the peak level of input
Package
The GD16522 is provided in 48 lead
power enhanced TQFP with heat slug on
bottom surface which is VEE potential.
Peak Level Monitor
An integrated analogue peak level detec-
tor circuit continuously monitors the input
data voltage swing.
The output from this circuit is conditioned
and is available as an analogue output
signal at the MON pin.
Data Sheet Rev.: 21
GD16522
Page 3 of 12
VCC
VCC VCC
50
50
50
From LINE
SDIP
50
VTT
DIREF
50
DIREFN
8k
50
+
-
26dB
8k
VTT
From LINE
SDIN
Figure 1.
DC Coupled Input (Ignoring internal offset
compensation)
Figure 4.
DC Coupled Outputs
VCC
VCC VCC
50
50
50
From LINE
SDIP
50
VEE
DIREF
50
DIREFN
8k
50
+
-
26dB
8k
VEE
From LINE
SDIN
Figure 2.
AC Coupled Input (Using internal offset
compensation)
Figure 5.
AC Coupled Outputs
PCTL
VCTL
39W
1
m
F
VCC
Figure 3.
Loop Filter
Data Sheet Rev.: 21
GD16522
Page 4 of 12
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