an Intel company
10 Gbit/s
Receiver,
CDR and DeMUX
GD16544
Preliminary
General Description
GD16544 is a 9.95328 Gbit/s Receiver
chip for use in SDH STM-64 and SONET
OC-192 optical communication systems.
GD16544 is a Clock and Data Recovery
IC with:
u
an on-chip VCO
u
a Bang-Bang Phase Detector
u
a 1:16 De-multiplexer
u
a Lock Detect
u
a Phase and Frequency Detector.
Clock and data are regenerated by using
GD16544 in a
Phase Lock Loop
(PLL)
with an external loop filter.
The VCO frequency is controlled by two
different Phase and Frequency Detectors
to ensure capture and lock to the line
data rate. When the frequency deviates
more than ±500 ppm from the reference
clock, GD16544 automatically switches
the phase and frequency detector into
the PLL loop. In the auto lock mode the
locking range is selectable between
±500 or ±2000 ppm.
The Lock Detector circuit monitors the
VCO frequency and determines when the
VCO is within the locking range. If in lock
VCO
VCTL
Timing Control
Features
it switches the Bang-Bang Phase
Detector into the PLL.
When the VCO frequency is within the
locking range, the Bang-Bang Phase De-
tector takes over. It controls the phase of
the VCO until the sampling point of data
is in the middle of the bit period, where
the eye opening is largest. A
±
40 mV
Decision Threshold Control
(DTC) is pro-
vided at the 10 Gbit/s input.
The 10 Gbit/s input data is retimed and
de-multiplexed by the 1:16 DeMUX. The
parallel output interface is synchronised
with the 622 MHz output clock.
GD16544 is manufactured in a Silicon Bi-
polar process.
l
l
Complete Clock and Data Recovery
IC with auto acquisition.
Low noise 10 GHz VCO with ±5 %
tuning range.
Digital controlled lock to data by a
Bang-Bang Phase Detector.
Automatic capture of the VCO
frequency by a true Phase and
Frequency Detector.
Locking range selectable between
±500 and ±2000 ppm.
Input Decision Threshold Control
(DTC):
±
40 mV.
1:16 DeMUX with differential
622 Mbit/s data outputs.
Open collector clock and data
outputs.
622 MHz Clock output.
155 or 622 MHz Reference Clock.
Single supply operation: -5.2 V.
Power dissipation: 2.9 W (typ).
Silicon Bipolar technology.
68 pin Multi Layer Ceramic (MLC)
package.
l
l
l
l
l
GD16544 uses a single -5.2 V supply
voltage.
l
The power dissipation is 2.9 W typical.
GD16544 is delivered in a
Multi Layer
Ceramic
(MLC) package, with internal
high-speed 50
W
transmission lines.
CKOUT
CKOUTN
l
l
l
l
l
DO0
DON0
DI
DIN
l
DTC
DTCN
Decision
Threshold
Control
Bang
Bang
Phase
Detector
1:16
Demultiplexer
Parallel
Output
Data
DO15
DON15
U
D
PCTL
POUT
Applications
l
REFCK
REFCKN
Phase
Frequency
Detector
1/4
PHIGH
Telecommunication systems:
– SDH STM-64
– SONET OC-192.
Fibre optic test equipment.
Submarine systems.
Lock
Detect
PLOW
l
LOCK
l
SEL3
SEL1
SEL2
TCK
RESET VDDO
VDD
VEE
VDDA
VEEA
Data Sheet Rev.: 05
Functional Details
The application of GD16544 is as re-
ceiver in SDH STM-64 and SONET
OC-192 optical communication systems.
It integrates:
u
a Voltage Controlled Oscillator (VCO)
u
a Clock and Data Recovery Circuit
u
a Lock Detect Circuit
u
a 1:16 DeMUX
u
a Phase and Frequency Detector
(PFD).
Loop Filter
The external loop filter is made using a
operational amplifier connected to output
pin (PHIGH and PLOW). The characte-
ristics of the phase lock loop are con-
trolled by the loop filter components
hence the op-amp is designed as an inte-
grator by a feedback capacitor and a re-
sistor. The gain-bandwidth of the op-amp
is larger than the required PLL bandwidth
in order not to limit the PLL. The recom-
mended op-amp is Analog Devices
(AD8042) with a gain-bandwidth of
160 MHz sufficient for PLL bandwidth up
to 50 MHz. The op-amp is used single
supplied by –5.2 V. See
Figure 1
for ap-
plication information.
The phase information from the Bang-
Bang phase detector are very high fre-
quency pulses (200 ps pulse width) at
output pins (PHIGH and PLOW). They
are open collector outputs with a 8 mA
current drive and are terminated exter-
nally by 100
W
to 0 V. A pre-filtering of
the phase pulses are applied by a paral-
lel 10 pF capacitor (see
Figure 1).
The PCB layout of the external loop filter
and the connecting lines to PHIGH,
PLOW and VCTL are critical for the jitter
performance of the component. The art-
work for the op-amp and the passive
components should be placed very close
to the pins of GD16544 in order to have
connecting lines as short as possible.
Ideally the loop filter components are
placed on the opposite side of the PCB
directly underneath GD16544. For more
layout suggestions see the 10 Gbit/s
evaluation board GD90244/255.
Alternatively the phase information is
also available at output pins (PCTL and
POUT) and are used with an external
passive loop filter in applications with a
low PLL bandwidth (< 1 MHz ) instead of
the above recommended active loop fil-
ter. The PCTL and POUT pins should al-
ways be terminated as shown in
Figure 1
also even though they are not actively
used in the PLL.
POUT is a high impendance input and
will be destroyed if connected directly
(lowohmic, <25 kW) to -2.5 V to 0 V.
lected by SEL1. In auto lock mode, the
lock range ±500 or ±2000 ppm is se-
lected by SEL2.
The Inputs
The input amplifier pin (DI/DIN) is de-
signed as a gain buffer stage with high
sensitivity and internal 50
W
resistors ter-
minated to 0 V. After retiming, the data is
de-multiplexed down to 622 Mbit/s by the
1:16 DeMUX. The input data is
de-multiplexed starting with DO0,
DO1...DO15 as the first received bits.
It is recommended to use the 10 Gbit/s
inputs differentially.
The 10 Gbit/s inputs (DI and DIN) are
not ESD protected
and extra precau-
tions are needed when handling these in-
puts. (Internal 50
W
resistors provide
some ESD hardness making the input
low impendance.)
The input voltage decision threshold is
adjustable by pin DTC and DTCN when
connected to a potentiometer. Adjusting
the resistor value of the meter controls
the current into DTC and DTCN. This DC
current is mirrored to the input pin (DI
and DIN) whereby the DC bias voltage at
the input is adjustable by
±40
mV. Opti-
mizing the input decision threshold im-
proves the system input sensitivity by
1-2 dB typical.
The input impedance into DTC and
DTCN is 1.5 kW and when not used they
should be de-coupled to 0 V by 100 nF.
The select inputs (SEL1-3, RESET and
TCK) are low speed inputs that can be
connected directly to the supply rails
(0 / -5.2 V).
VCO
The VCO is an LC-type differential oscil-
lator at 10 GHz, voltage controlled by pin
VCTL and with a tuning range of approxi-
mately ±5 %.
With the VCTL voltage at approximately
-3.5 V the VCO frequency is fixed at
9.953 GHz and by changing the voltage
from 0 to -5.2 V the frequency is con-
trolled from 8.9 GHz to 10.2 GHz. The
modulation bandwidth of VCTL is
90 MHz (see VCO Measurement on
page 13
).
PFD
The PFD, ensures predictable locking
conditions for the GD16544. It is used
during acquisition and pulls the VCO into
the locking range where the Bang-Bang
Phase Detector acquires lock to the in-
coming bit-stream. The PFD is made with
digital set/reset cells giving it a true
phase and frequency characteristic. The
reference clock input (REFCK/REFCKN)
to the PFD is differential and selectable
between 155 MHz or 622 MHz by SEL3.
The reference clock input has 50
W
inter-
nal termination resistors to 0 V. The ref-
erence clock is typically an X-tal
oscillator type as shown on
Figure 1.
The
reference clock input should be used dif-
ferential for best performance.
The Outputs
The data outputs, the clock output and
LOCK are differential open collector out-
puts with an 8 mA output current. They
are terminated externally with a resistor
(R) to 0 V and the output voltage swing is
V = -50 × 8 mA = -400 mV with R = 50
W.
Increasing the resistor increases the out-
put voltage and reduces the bandwidth.
The open collector outputs can be
configurated as CML or ECL compatible
using external circuit. (See item
“622 Mbit/s Output Interface” on
page 6).
When interfacing LDVS see item “Inter-
facing to a Positive Supply Interface
Technology” on next page.
Bang-Bang Phase Detector
The Bang-Bang phase detector is de-
signed as a true digital type producing a
binary output. It samples the incoming
data prior to, in the vicinity of and after
any potential bit transition.
When a transition has occurred, these
three samples tell whether the VCO clock
leads or lags the data. The binary output
is filtered through the (low pass) loop fil-
ter, performing an integration of all poten-
tial bit transitions. Hence the PLL is
controlled by the bit transition point.
Lock Detect Circuit
The lock detect circuit continuously moni-
tors the difference between the reference
clock and the VCO clock. If they are
apart by more than ±500 (or ±2000 ppm),
it switches the PFD into the PLL, to pull it
back into the locking range. The status of
the lock circuit is given by output pin
(LOCK). Manual or automatic lock is se-
Data Sheet Rev.: 05
GD16544
Page 2 of 16
Timing
The timing between GD16544 and the
system ASIC at 622 Mbit/s is controlled
by the 622 MHz output clock synchro-
nized with the output data. The clock is
used as the input clock to the ASIC,
clocking the input data into 16 parallel
shift registers. The timing relation be-
tween clock and data is given by the AC
Characteristics.
External Circuit
The external circuits needed to make
GD16544 work as a complete clock and
data recovery with automatic acquisition
are:
u
Active loop filter with op-amp
u
An x-tal oscillator at 155 MHz or
622 MHz
u
Pull up resistors on all outputs and
de-coupling capacitors.
In the layout of the printed circuit board
the 10 Gbit/s inputs are connected with
50
W
Micro Strip Lines
(MLS) to the
high-speed connector. The micro strip
lines should be as short as possible
(<15 mm) with a plain and solid ground
plan below. The layout artwork for the
loop filter is placed preferable on the op-
posite side of the component with very
short connections to the pins of
GD16544. The 100
W
resistors and
10 pF capacitor connected from PHIGH
and PLOW to 0 V should be placed very
close to the package pin no. 50 and 53.
The environment around the loop filter
and the 10 Gbit/s inputs is noise sensi-
tive and no noise generating lines are al-
lowed in this area.
The power supply to GD16544 should be
separated from other noise generation
components on the board and be de-
coupled as shown on Figure 2. DC-DC
converters are only allowed on the same
board if proper noise filtering is applied.
Package
GD16544 is packaged in a 68 pin Multi
Layer Ceramic package with internal
50
W
transmission lines. The cavity of the
package is down for easy cooling with a
mounted head spreader on top.
Thermal Condition
The component dissipates 2.9 W with a
–5.2 V voltage supply and need forced
cooling with a heat sink thermally con-
nected to the heat spreader. The thermal
connection should ensure the case tem-
perature in the range from 0 to 70 °C with
the given ambient conditions e.g. tempe-
rature and air flow etc.
Mounting and Layout
of PCB.
The component can be mounted on a
standard FR4 epoxy printed circuit board
when special attention is taken in the lay-
out and in the mounting of the compo-
nent.
It is important for the performance of the
component that the leads of pin DI and
DIN (10 Gbit/s inputs) are made very
short (<1 mm) when mounted on the
board. Best way to make the leads short
is to cut a hole in the PCB and to mount
the component inside the hole. The
length of the two critical leads is reduced
to less than 0.5 mm whereas the rest of
the leads are kept at 2-4 mm in order for
mechanical stability. On the backside
the head spreader is thermally mounted
to a metal block with heat sink compound
(see paragraph “Mounting of Component
on PCB” on
page 14).
In cases where the
above mounting technical is not applica-
ble, the component can be mounted di-
rectly on the board with bend leads
accepting longer leads for the 10 Gbit/s
inputs e.g. reduced input sensitivity and
reflection.
The component is available with straight
leads and with gullwing leads, see the
package outline drawings.
Power Noise Rejection
In a noisy environment special attention
must be taken as described above to op-
timize the jitter performance and to re-
duce the input sensitivity penalty from
injected noise. The
Power Supply Rejec-
tion Ratio
(PSRR) is improved by adding
a serial resistor (330
W)
and capacitor
(33 nF) from the positive input of the
op-amp to the VEEA power pin (no. 52)
as shown in
Figure 1.
Interfacing to a Positive
Supply Interface Technology
The data outputs (DO0-15) and the clock
output (CKOUT/N) are externally termi-
nated with top resistors. When interfacing
a positive supplied interface technology
(e.g. LVDS) the external resistors can be
terminated directly to the positive supply.
A version of GD16544 (GD16544/HV-
68XX) is offered with all data outputs and
the clock output DC tested for a minimum
breakdown voltage of 8 V.
The maximum allowed output voltage on
all outputs is 2.6 V.
Data Sheet Rev.: 05
GD16544
Page 3 of 16
Applications
1
0V
0V
VDDO
TCK / 45
RESET / 41
VDD
0V
0V
-5.2V
50W
50W 50W
50W
1
0
0V
-5.2V
0V
-5.2V
50
W
MSL
VDD
50
W
MSL
SEL1 / 54
SEL2 / 56
SEL3 / 1
61 / DOO
62 / DOON
50
W
MSL
50
W
MSL
1
0
39 / DO15
DI / 42
DIN / 44
DTC / 17
40 / DO15N
15 / CKOUT
16 / CKOUTN
50
W
MSL
50
W
MSL
GD16544
10Gb/s
CML Driver
50
W
MSL
50
W
MSL
50W
0V
50W
0V
VDD
220
10k
0V
DTCN / 18
59 / LOCK
14
8
7
330
43
100nF
REFCK / 57
220
-5.2V
330W
0V
100W
100nF
+
-
-5.2V
VREF
XO-PECL
155/622 MHz
KVG
-5.2V
49 / PCLT
RECKN / 58
47 / POUT
100nF
-5.2V
220
-5.2V
3.3kW
53 / PLOW
VCTL / 48
VEEA / 52
-5.2V
-5.2V
0V
33nF
0V
50 / PHIGH
VEE
-5.2V
2k2
2k2
0.1
m
F
10pF
100W
0V
330W
AD8042
+
-
-5.2V
100W
0.1
m
F
100W
0V
Figure 1.
Application Information.
VDD
VEE
VDDO
VEEA
Pin4
C
C
Pin9
Pin14
C
Pin21
C
Pin26
C
Pin31
C
Pin36
C
Pin43
C
Pin48
C
Pin55
C
Pin60
C
Pin65
C
10
m
F
Pin51
C
Pin35
C
VDDA
10
m
F
C is 10nF parallel with 100pF.
VEE pins 34/68; VEEA pin 52
Figure 2.
De-coupling Supply.
GD16544
Page 4 of 16
Data Sheet Rev.: 05
Applications Continued
10 Gbit/s Input Interface
GD16544
0V
50W
50W
0V
50W
DI
DIN
50
W
MSL
0/-0.4V
0/-0.4V
Postamplifier
-5.2V
>16mA
Figure 3.
10 Gbit/s Input (DI/DIN), DC Coupled
GD16544
0V
50W
50W
-5.2V
220W
DI
DIN
100nF
220W
-5.2V
-5.2V
50
W
MSL
Post-
amplifier
Figure 4.
10 Gbit/s Input (DI/DIN), AC Coupled
Data Sheet Rev.: 05
GD16544
Page 5 of 16
单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
