3.3V 128K (8Kx16-BIT)
CACHE-TAG SRAM
For 3.3V Processors
Integrated Device Technology, Inc.
PRELIMINARY
IDT71V218
FEATURES:
• 8K x 16 Configuration
– 14 Common I/O TAG Bits
– 2 Separate I/O Status Bits (VLD and DTY)
• Optimized for 256KB cache and 4GB cacheable space
• High-Speed Address-to-Match comparison times
– 10/12/15ns
• Optional inclusion of Valid bit in Match output
• Asynchronous Read, Match, and Reset operations
• Synchronous Write operation
•
RESET
pin invalidates all Tag entries
• Dual Chip selects for easy depth expansion with no
performance degredation
• 3.3V power supply
• ZZ pin available to place device in low-power mode
• 48-pin Shrink Small Outline Package (SSOP)
DESCRIPTION:
The IDT71V218 is a 131,072-bit Cache Tag Static RAM,
organized 8K x 16. There are fourteen common I/O TAG bits,
with the remaining two bits used as status bits. A 14-bit
comparator is on-chip to allow fast comparison of the fourteen
stored TAG bits and the current Tag input data. An active
HIGH MATCH output is generated when these two groups of
data are the same for a given address. This high-speed
MATCH signal is available as soon as 10ns after the address
is presented to the TAG bit inputs.
There are two separate I/O status bits, VLD and DTY.
When the input pin VALM is HIGH, the VLD bit is used to
internally qualify the MATCH output. If VALM is LOW, the VLD
bit is not internally involved in the MATCH decision , but is
available for use by outside system logic. The DTY bit is not
used for internal decision making in the IDT71V218.
Match and Read operations are both asynchronous in
order to provide the fastest access times possible, while Write
operations are synchronous for ease of system timing. The
asynchronous
RESET
pin, when held LOW, will reset all status
bits in the array for easy invalidation of all Tag addresses.
The IDT71V218 is a full 3.3V device which uses a single
3.3V power supply to offer compliance with 3.3V LVTTL Logic
levels. The ZZ pin offers a low-power Sleep mode to reduce
power consumption and provide system power savings.
The IDT71V218 is fabricated using IDT's high-performance,
high-reliability 3.3V CMOS technology and is offered in a
space-saving 48-pin Shrink Small Outline Package (SSOP)
package.
FUNCTIONAL BLOCK DIAGRAM
CLK
A0 - A12
13
ADDRESS
REGISTER
1
0
Sel
WRITE
DRIVER
Enable
DTY
IN
VLD
IN
2
INPUT
REGISTER
8K x 2
MEMORY
ARRAY
Reset
SENSE
AMPS
2
VLD
DTY
OUT
VLD
OUT
INPUT
REGISTER
WRITE
DRIVER
Enable
8K x 14
MEMORY
ARRAY
SENSE
AMPS
14
TAG0 - TAG13
OE
WE
COMPARE
WRITE
REGISTER
MATCH
CS1
CS2
POWERDOWN
ZZ
RESET
VALM
RESET
PULSE GEN
3196 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996
Integrated Device Technology, Inc.
JANUARY 1997
DSC-3196/1
14.4
1
IDT71V218
3.3V CMOS 8Kx16 CACHE-TAG RAM
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS
A
0
– A
12
Address Inputs
Chip Selects
Write Enable
Output Enable
Status Bit Reset
Sleep Mode Control Pin
Status Input Bit (Valid)
Status Input Bit (Dirty)
Input
Input
Input
Input
Input
Input
Input
Input
VALM
CLK
TAG
0
– TAG
13
VLD
OUT
DTY
OUT
MATCH
V
DD
V
SS
Valid-included-with-Match
System Clock
Tag Data Input/Outputs
Status Output Bit (Valid)
Status Output Bit (Dirty)
Match
+3.3V Power (4 pins)
Ground (4 pins)
Input
Input
I/O
Output
Output
Output
Pwr
Gnd
3196 tbl 01
CS
1
, CS
2
WE
OE
RESET
ZZ
VLD
IN
DTY
IN
PIN CONFIGURATION
A
0
A
1
A
2
VALM
ZZ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Com’l.
–0.5 to +4.6
–0.5 to V
DD
+0.5
0 to +70
–55 to +125
–55 to +125
1.0
50
Unit
V
V
°C
°C
°C
W
mA
RESET
OE
CS
2
CS
1
WE
SO48-1
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CLK
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
DTY
IN
VLD
IN
V
SS
V
DD
TAG
13
TAG
12
TAG
11
V
DD
V
SS
TAG
10
TAG
9
TAG
8
TAG
7
TAG
6
TAG
5
V
DD
MATCH
V
SS
TAG
4
TAG
3
VLD
OUT
DTY
OUT
V
SS
V
DD
TAG
2
TAG
1
TAG
0
3196 drw 02
V
TERM(2)
V
TERM(3)
T
A
T
BIAS
T
STG
P
T
I
OUT
NOTES:
3196 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
DD
and Input terminals only.
3. I/O terminals.
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
DD
GND
V
IH
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
Min. Typ.
3.135
0
2.0
2.0
–0.3
(1)
3.3
0
—
—
—
Max. Unit
3.465
0
5.0
V
DD
+0.3
V
V
V
V
V
SSOP
TOP VIEW
0.8
NOTE:
3196 tbl 03
1. V
IL
(min.) = –1.5V for pulse width less than t
CYC
/2, once per cycle.
CAPACITANCE
(T
A
= +25°C, f = 1.0 MHz)
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Commercial
Temperature
0°C to +70°C
GND
0V
V
DD
3.3V
±
5%
3196 tbl 04
Symbol
C
IN
C
I/O
C
OUT
Parameter
(1)
Input Capacitance
Input/Output
Capacitance
Output Capacitance
Condition
V
IN
= 3dV
V
I/O
= 3dV
V
OUT
= 3dV
Max.
6
7
7
Unit
pF
pF
pF
NOTE:
3196 tbl 05
1. This parameter is determined by device characterization but is not produc-
tion tested.
14.4
2
IDT71V218
3.3V CMOS 8Kx16 CACHE-TAG RAM
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
(V
DD
= 3.3V
±
5%, T
A
= 0 to 70°C)
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Condition
V
DD
= Max., V
IN
= GND to V
DD
V
DD
= Max.,
CS
1
= V
IH,
V
OUT
= GND to V
DD
I
OL
= 8mA, V
DD
= Min.
I
OH
= –8mA, V
DD
= Min.
Min.
—
—
—
2.4
IDT71V218
Typ.
—
—
—
—
Max.
5
5
0.4
—
Unit
µA
µA
V
V
3196 tbl 06
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING
TEMPERATURE AND SUPPLY VOLTAGE RANGE
(1, 2)
(V
DD
= 3.3V
±
5%, T
A
= 0 to 70°C)
Symbol
I
DD
I
SB
I
ZZ
Parameter
Operating Power
Supply Current
Standby Power
Supply Current
Full Sleep Mode Power
Supply Current
Test Condition
ZZ
≤
V
IL
,
CS
1
≤
V
IL
, CS
2
≥
V
IH
,
RESET
≥
V
IH
Outputs Open, V
DD
= Max., f = f
MAX
(3)
ZZ
≥
V
IH
, V
IN
≥
V
IH
or
≤
V
IL
V
DD
= Max., f = f
MAX
(3)
ZZ
≥
V
HD
, V
IN
≥
V
HD
or
≤
V
LD
V
DD
= Max., f = 0
(3)
71V218S10
175
15
5
71V218S12
165
15
5
71V218S15 Unit
155
15
5
mA
mA
mA
3196 tbl 07
NOTES:
1. All values are maximum guaranteed values.
2. V
HD
= V
DD
- 0.2V, V
LD
= 0.2V
3. f
MAX
=1/t
CYC
(CLK cycling at f
MAX
, address inputs cycling at 1/3 f
MAX
). f = 0 means no input or I/O signals are switching.
FUNCTIONAL TRUTH TABLE
(1)
MODE
Sleep
Reset
Deselect
Deselect
Read
Write
Write Status Only
Match (see below)
TAG VLD
IN
DTY
IN
VLD
OUT
DTY
OUT
Hi-Z
Hi-Z
Hi-Z
Hi-Z
OUT
IN
OUT
IN
X
X
X
X
X
IN
IN
X
X
X
X
X
X
IN
IN
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
OUT
VLD
IN
VLD
IN
OUT
Hi-Z
Hi-Z
Hi-Z
Hi-Z
OUT
DTY
IN
DTY
IN
OUT
OE
X
X
X
X
L
H
L
H
WE CS1
X
H
X
X
H
L
L
H
X
X
H
X
L
L
L
L
CS2
X
X
X
L
H
H
H
H
ZZ
H
L
L
L
L
L
L
L
RESET
X
L
H
H
H
H
H
H
VALM
X
X
X
X
X
X
X
-
MATCH
Hi-Z
Hi-Z
Hi-Z
Hi-Z
U
U
U
-
3196 tbl 09
NOTES:
1. "H" = V
IH
, "L" = V
IL
, "X" = Don't Care, Hi-Z = High Impedance, U = Output is driven, but level is undefined.
MATCH TRUTH TABLE
(1, 2)
MODE
Simple Match
Simple Mismatch
Invalid Entry
Match on Valid Entry
Mismatch on Valid Entry
TAG
(IN)
= ADDRESSED DATA
≠
ADDRESSED DATA
X
= ADDRESSED DATA
≠
ADDRESSED DATA
VALM
L
L
H
H
H
VLD
OUT
X
X
L
H
H
MATCH
H
L
L
H
L
3196 tbl 10
NOTES:
1.
OE
=
WE
= CS2 =
RESET
= High.
CS1
= ZZ = Low
2. "H" = V
IH
, "L" = V
IL
, "X" = Don't Care.
14.4
3
IDT71V218
3.3V CMOS 8Kx16 CACHE-TAG RAM
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
3ns
1.5V
1.5V
See Figures 1, 2, 3, and 4
3196 tbl 08
3.3V
320
Ω
DATA
OUT
350
Ω
30pF*
DATA
OUT
350
Ω
3.3V
320
Ω
15pF*
3196 drw 03
3196 drw 04
Figure 1. AC Test Load
TAG Outputs
Figure 2. AC Test Load
MATCH, VLD and DTY Outputs
3.3V
320
Ω
DATA
OUT
350
Ω
5pF*
4
3
∆
t
AMV,
∆
t
ATV, etc.
(Typical, ns)
2
1
3196 drw 05
0
Figure 3. AC Test Load
(for t
LZ
and t
HZ
parameters)
25
50
75
100
3196 drw 06
∆
C
L
(pF)
Figure 4. Capactive Derating
*Includes scope and jig capacitances
14.4
4
IDT71V218
3.3V CMOS 8Kx16 CACHE-TAG RAM
PRELIMINARY
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(V
DD
= 3.3V
±
5%, T
A
= 0 to 70°C)
Symbol
MATCH Cycle
t
AMV
t
TMV
t
CMV
t
CMLZ
(1)
t
CMHZ
(1)
t
AMH
t
TMH
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 3) by device characterization, but is not production tested.
Parameter
Address to MATCH Valid
Tag Input to MATCH Valid
Chip Enable to MATCH Valid
Chip Enable to MATCH in Low-Z
Chip Enable to MATCH in High-Z
MATCH Valid Hold from Address Change
MATCH Valid Hold from Tag Input Change
IDT71V218S10
Min.
Max.
—
—
—
2
0
2
2
10
10
10
—
6
—
—
IDT71V218S12
Min.
Max.
—
—
—
2
0
2
2
12
12
12
—
6
—
—
IDT71V218S15
Min.
Max.
—
—
—
2
0
2
2
15
15
15
—
7
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
3196 tbl 11
AC ELECTRICAL CHARACTERISTICS
(V
DD
= 3.3V
±
5%, T
A
= 0 to 70°C)
Symbol
Read Cycle
t
ATV
t
CTV
t
CLZ
(1)
t
CHZ
(1)
t
OE
t
OLZ
(1)
t
OHZ
(1)
t
ATH
t
ASV
t
CSV
t
ASH
Parameter
Address to Tag Valid
Chip Enable to Tag Valid
Chip Enable to Tag and Status Bits in Low-Z
Chip Enable to Tag and Status Bits in High-Z
Output Enable to Tag Bits Valid
Output Enable to Tag Bits in Low-Z
Output Enable to Tag Bits in High-Z
Tag Bit Hold from Address Change
Address to Status Valid
Chip Enable to Status Valid
Status Bit Hold from Address Change
IDT71V218S10
Min. Max.
—
—
2
0
—
0
0
2
—
—
2
13
11
—
6
6
—
6
—
10
10
—
IDT71V218S12
Min.
Max.
—
—
2
0
—
0
0
2
—
—
2
15
13
—
6
7
—
6
—
12
12
—
IDT71V218S15
Min.
Max.
—
—
2
0
—
0
0
2
—
—
2
17
15
—
7
7
—
7
—
15
15
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3196 tbl 12
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 3) by device characterization, but is not production tested.
AC ELECTRICAL CHARACTERISTICS
(1)
(V
DD
= 3.3V
±
5%, T
A
= 0 to 70°C)
Symbol
t
S
t
H
t
SA
t
HA
t
KMH
t
KRTV
(3)
t
KWSV
(3)
t
KRSV
(3)
t
KSH
(2)
t
OW
t
WO
Parameter
IDT71V218S10
Min.
Max.
3
1
3
1
0
—
—
—
2
10
5
—
—
—
—
—
12
12
12
—
—
—
IDT71V218S12
Min.
Max.
3
1
3
1
0
—
—
—
2
10
5
—
—
—
—
—
14
14
14
—
—
—
IDT71V218S15
Min.
Max.
3
1
3
1
0
—
—
—
2
12
6
—
—
—
—
—
16
16
16
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3196 tbl 13
Write Cycle and Clock Parameters
WE
, Chip Enable, and Input Data Set-up Time
WE
, Chip Enable, and Input Data Hold Time
Address Set-up Time (Write Cycle Only)
Address Hold Time (Write Cycle Only)
CLK HIGH Write to MATCH Invalid
CLK HIGH Read to Tag Bits Valid
CLK HIGH Write to Status Outputs Valid
CLK HIGH Read to Status Outputs Valid
Status Output Hold from CLK HIGH (Write Cycle)
OE
HIGH before Write
End of Write to
OE
Asserted
NOTES:
1. All Write cycles are synchronous and referenced from rising CLK.
2. This parameter is guaranteed by device characterization, but is not production tested.
3. Addresses are stable prior to CLK transition HIGH.
14.4
5
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