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Dual High Speed PECL Comparators
ADCMP561/ADCMP562
FEATURES
Differential PECL compatible outputs
700 ps propagation delay input to output
75 ps propagation delay dispersion
Input common-mode range: –2.0 V to +3.0 V
Robust input protection
Differential latch control
Internal latch pull-up resistors
Power supply rejection greater than 85 dB
700 ps minimum pulse width
1.5 GHz equivalent input rise time bandwidth
Typical output rise/fall time of 500 ps
ESD protection > 4kV HBM, >200V MM
Programmable hysteresis
FUNCTIONAL BLOCK DIAGRAM
HYS*
NONINVERTING
INPUT
Q OUTPUT
ADCMP561/
ADCMP562
INVERTING
INPUT
Q OUTPUT
*ADCMP562 ONLY
Figure 1.
V
DD 1
QA
2
04687-0-001
LATCH ENABLE
INPUT
LATCH ENABLE
INPUT
20
V
DD
19
QB
18
QB
APPLICATIONS
Automatic test equipment
High speed instrumentation
Scope and logic analyzer front ends
Window comparators
High speed line receivers
Threshold detection
Peak detection
High speed triggers
Patient diagnostics
Disk drive read channel detection
Hand-held test instruments
Zero-crossing detectors
Line receivers and signal restoration
Clock drivers
QA
1
QA
2
V
DD
LEA
3
4
16
15
14
QB
QB
GND
LEB
LEB
V
CC
04687-0-002
QA
3
V
DD 4
LEA
5
LEA
6
V
EE 7
–INA
8
+INA
9
HYSA
10
ADCMP562
TOP VIEW
(Not to Scale)
17
GND
16
LEB
15
LEB
14
V
CC
13
–INB
04687-0-003
ADCMP561
TOP VIEW
(Not to Scale)
13
12
11
10
9
LEA
5
V
EE 6
–INA
7
+INA
8
–INB
+INB
12
+INB
11
HYSB
Figure 2. ADCMP561 16-Lead QSOP
Figure 3. ADCMP562 20-Lead QSOP
GENERAL DESCRIPTION
The ADCMP561/ADCMP562 are high speed comparators
fabricated on Analog Devices’ proprietary XFCB process. The
devices feature a 700 ps propagation delay with less than 75 ps
overdrive dispersion. Dispersion, a measure of the difference in
propagation delay under differing overdrive conditions, is a
particularly important characteristic of comparators. A separate
programmable hysteresis pin is available on the ADCMP562.
A differential input stage permits consistent propagation delay
with a wide variety of signals in the common-mode range from
−2.0 V to +3.0 V. Outputs are complementary digital signals that
are fully compatible with PECL 10 K and 10 KH logic families.
The outputs provide sufficient drive current to directly drive
transmission lines terminated in 50 Ω to V
DD
− 2 V. A latch
input, which is included, permits tracking, track-and-hold, or
sample-and-hold modes of operation. The latch input pins
contain internal pull-ups that set the latch in tracking mode
when left open.
The ADCMP561/ADCMP562 are specified over the industrial
temperature range (−40°C to +85°C).
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
ADCMP561/ADCMP562
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Considerations.............................................................. 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 8
Timing Information ....................................................................... 10
Application Information................................................................ 11
Clock Timing Recovery............................................................. 11
Optimizing High Speed Performance ..................................... 11
Comparator Propagation Delay Dispersion ........................... 11
Comparator Hysteresis .............................................................. 12
Minimum Input Slew Rate Requirement ................................ 12
Typical Application Circuits.......................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
7/04—Data Sheet Changed from Rev. 0 to Rev. A
Changes to Specification Table ....................................................... 4
Changes to Figure 14........................................................................ 9
Changes to Figure 21...................................................................... 12
Changes to Figure 23...................................................................... 13
4/04—Revision 0: Initial Version
Rev. A | Page 2 of 16
ADCMP561/ADCMP562
SPECIFICATIONS
V
CC
= +5.0 V, V
EE
= −5.2 V, V
DD
= +3.3 V, T
A
= −40°C to +85°C. Typical values are at T
A
= +25°C, unless otherwise noted.
Table 1. Electrical Characteristics
Parameter
DC INPUT CHARACTERISTICS
Input Voltage Range
Input Differential Voltage
Input Offset Voltage
Input Offset Voltage Channel Matching
Offset Voltage Tempco
Input Bias Current
Input Bias Current Tempco
Input Offset Current
Input Capacitance
Input Resistance, Differential Mode
Input Resistance, Common Mode
Active Gain
Common-Mode Rejection Ratio
Hysteresis
LATCH ENABLE CHARACTERISTICS
Latch Enable Voltage Range
Latch Enable Differential Voltage Range
Latch Enable Input High Current
Latch Enable Input Low Current
LE Voltage, Open
LE Voltage, Open
Latch Setup Time
Latch Hold Time
Latch-to-Output Delay
Latch Minimum Pulse Width
DC OUTPUT CHARACTERISTICS
Output Voltage—High Level
Output Voltage—Low Level
Rise Time
Fall Time
AC PERFORMANCE
Propagation Delay
Propagation Delay Tempco
Prop Delay Skew—Rising Transition to
Falling Transition
Within Device Propagation Delay Skew—
Channel-to-Channel
Overdrive Dispersion
Overdrive Dispersion
Slew Rate Dispersion
Pulse Width Dispersion
Duty Cycle Dispersion
Common-Mode Voltage Dispersion
Symbol
Conditions
Min
−2.0
−5
−10.0
Typ
Max
3.0
+5
+10.0
Unit
V
V
mV
mV
µV/°C
µA
nA/°C
µA
pF
kΩ
kΩ
dB
dB
mV
V
V
µA
µA
V
V
ps
ps
ps
ps
V
V
ps
ps
ps
ps
ps/°C
ps
ps
ps
ps
ps
ps
ps
ps
V
OS
∆V
OS
/d
T
I
IN
V
CM
= 0 V
−IN = −2 V, +IN = +3 V
−10.0
C
IN
A
V
CMRR
V
CM
= −2.0 V to +3.0 V
R
HYS
= ∞
V
DD
− 2.0
0.4
−300
−300
V
DD
− 0.2
V
DD
/2 − 0.2
±2.0
±2.0
2.0
±3
0.5
±1.0
0.75
750
1800
63
80
±1.0
+10.0
t
S
t
H
t
PLOH
, t
PLOL
t
PL
V
OH
V
OL
t
R
t
F
t
PD
∆t
PD
/d
T
@ V
DD
@ V
DD
−2.0 V
Latch inputs not connected
Latch inputs not connected
V
OD
= 250 mV
V
OD
= 250 mV
V
OD
= 250 mV
V
OD
= 250 mV
PECL 50 Ω to V
DD
− 2.0 V
PECL 50 Ω to V
DD
− 2.0 V
10% to 90%
10% to 90%
V
OD
= 1 V
V
OD
= 20 mV
V
OD
= 1 V
V
OD
= 1 V
V
OD
= 1 V
20 mV ≤ V
OD
≤ 100 mV
100 mV ≤ V
OD
≤ 1.5 V
0.4 V/ns ≤ SR ≤ 1.33 V/ns
700 ps ≤ PW ≤ 10 ns
33 MHz, 1 V/ns, 0.5 V
1 V swing, −1.5 V ≤ V
CM
≤ +2.5 V
V
DD
V
DD
/2
250
250
600
500
V
DD
2.0
+300
+300
V
DD
+ 0.1
V
DD
/2 + 0.2
V
DD
− 1.15
V
DD
− 1.95
550
470
700
830
0.25
50
50
75
75
50
25
15
10
V
DD
− 0.81
V
DD
− 1.54
Rev. A | Page 3 of 16
ADCMP561/ADCMP562
Parameter
AC PERFORMANCE (continued)
Equivalent Input Rise Time Bandwidth
1
Maximum Toggle Rate
Minimum Pulse Width
RMS Random Jitter
Unit-to-Unit Propagation Delay Skew
POWER SUPPLY
Positive Supply Current
Negative Supply Current
Logic Supply Current
Logic Supply Current
Positive Supply Voltage
Negative Supply Voltage
Logic Supply Voltage
Power Dissipation
Power Dissipation
DC Power Supply Rejection Ratio—V
CC
DC Power Supply Rejection Ratio—V
EE
DC Power Supply Rejection Ratio—V
DD
HYSTERESIS (ADCMP562 Only)
Hysteresis
Symbol
BW
EQ
PW
MIN
Conditions
0 V to 1 V swing, 2 V/ns
>50% output swing
∆t
PD
< 25 ps
V
OD
= 400 mV, 1.3 V/ns, 312 MHz,
50% duty cycle
Min
Typ
1500
800
700
1.0
100
I
VCC
I
VEE
I
VDD
V
CC
V
EE
V
DD
P
D
PSRR
VCC
PSRR
VEE
PSRR
VDD
R
HYS
= 19.5 kΩ
R
HYS
= 8.0 kΩ
@ +5.0 V
@ −5.2 V
@ 3.3 V without load
@ 3.3 V with load
Dual
Dual
Dual
Dual, without load
Dual, with load
2
10
6
45
4.75
−4.96
2.5
130
180
3.2
22
9
60
5.0
−5.2
3.3
160
220
85
85
85
20
70
5
28
13
70
5.25
−5.45
5.0
190
250
Max
Unit
MHz
MHz
ps
ps
ps
mA
mA
mA
mA
V
V
V
mW
mW
dB
dB
dB
mV
mV
1
Equivalent input rise time bandwidth assumes a first-order input response and is calculated by the following formula: BW
EQ
= 0.22/√ (tr
COMP2
– tr
IN2
), where tr
IN
is the
20/80 input transition time applied to the comparator and tr
COMP
is the effective transition time as digitized by the comparator input.
Rev. A | Page 4 of 16
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