512Mb : x32 TwinDie Mobile SDRAM Addendum
Features
Mobile SDRAM
MT48LC16M32L2 – 4 Meg x 32 x 4 Banks
MT48V16M32L2 – 4 Meg x 32 x 4 Banks
MT48H16M32L2 – 4 Meg x 32 x 4 Banks
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Low voltage power supply
Partial array self refresh power-saving mode
Temperature compensated self refresh (TCSR)
Deep power-down mode
Programmable output drive strength
Fully synchronous; all signals registered on positive
edge of system clock
Internal pipelined operation; column address can
be changed every clock cycle
Internal banks for hiding row access/precharge
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto precharge, includes concurrent auto
precharge, and auto refresh modes
Self refresh mode; standard and low power
64ms, 8,192-cycle refresh
LVTTL-compatible inputs and outputs
Operating temperature range
Industrial (-40°C to +85°C)
Supports CAS latency of 1, 2, 3
Addendum Changes
The standard 256Mb SDRAM Mobile x32 data sheets
should be referenced for a complete description of
SDRAM functionality and operating modes. This
addendum data sheet will concentrate on the key dif-
ferences required to support the enhanced options of
the TwinDie configuration.
The Micron 256Mb Mobile X32 data sheet provides full
specifications and functionality unless specified
herein.
Table 1:
Speed
Grade
-8
-10
Key Timing Parameters
Clock
Frequency
125 MHz
100 MHz
Access Time Access Time
at CL = 3
at CL = 2
7.5ns
7.5ns
8.5ns
8.5ns
Table 2:
Configuration
16 Meg x 32
4 Meg x 32 x 4 banks
8K
8K (A0–A12)
4 (BA0, BA1)
512 (A0–A8)
Options
• V
DD
/V
DD
Q
3.3V/3.3V
2.5V/2.5V
1.8V/1.8V
• Configuration
16M32 stacked die
• Package/ballout
Plastic package 90-ball FBGA
(8mm x 13mm) (standard)
Plastic package 90-ball FBGA
(8mm x 13mm) (lead-free)
• Timing (cycle time)
8ns at CL3 (125 MHz)
10ns at CL3 (100 MHz)
• Temperature
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Marking
LC
V
H
L2
F5
B5
Architecture
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
-8
-10
No Marking
IT
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512Mb Mobile SDRAM_TwinDie_x32.fm - Rev. C 6/05 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
512Mb : x32 TwinDie Mobile SDRAM Addendum
General Description
General Description
The 512Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing
536,870,912 bits. It is internally configured by stacking two 256Mb, 8 Meg x 32 devices.
Each of these 256Mb devices is configured as a quad bank DRAM with a synchronous
interface. They are organized with 32 DQs with 4 banks of 67,108,864 bits, comprising of
8,192 rows by 512 columns by 32 bits wide.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select
the bank; A0-A12 select the row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4, or 8
locations, or the full page, with a burst terminate option. An auto precharge function
may be enabled to provide a self-timed row precharge that is initiated at the end of the
burst sequence.
The 512Mb SDRAM uses an internal pipelined architecture to achieve high-speed opera-
tion. This architecture is compatible with the 2n rule of prefetch architectures, but it also
allows the column address to be changed on every clock cycle to achieve a high-speed,
fully random access. Precharging one bank while accessing one of the other three banks
will hide the precharge cycles and provide seamless, high-speed, random-access opera-
tion.
The 512Mb SDRAM is designed to operate in 3.3V, 2.5V, and 1.8V memory systems. An
auto refresh mode is provided, along with a power-saving, power-down mode. All inputs
and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating performance, including the abil-
ity to synchronously burst data at a high data rate with automatic column-address gen-
eration, the ability to interleave between internal banks to hide precharge time, and the
capability to randomly change column addresses on each clock cycle during a burst
access.
Prior to normal operation, the SDRAM must be initialized. The following sections pro-
vide detailed information covering die intitialization, register definition, command
descriptions, and device operation on a per die basis unless otherwise noted.
This addendum documents any variances for the 512Mb: x32 Mobile SDRAM from the
256Mb: x32 Mobile SDRAM specification. Please refer to the 256Mb: x32 Mobile SDRAM
data sheet on Micron’s Web site for additional details on the part functionality.
Commands
AUTO REFRESH
AUTO REFRESH is used during normal operation of the SDRAM and is analogous to
CAS#-BEFORE-RAS# (CBR) REFRESH in conventional DRAMs. This command is non-
persistent, so it must be issued each time a refresh is required. All active banks must be
PRECHARGED prior to issuing a AUTO REFRESH command. The AUTO REFRESH com-
mand should not be issued until the minimum
t
RP has been met after the PRECHARGE
command as shown in the operations section.
The addressing is generated by the internal refresh controller. This makes the address
bits “Don’t Care” during an AUTO REFRESH command. The 512Mb TwinDie™ Mobile
SDRAM requires 8,192 AUTO REFRESH cycles every 64ms (
t
REF). Providing a distributed
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512Mb Mobile SDRAM_TwinDie_x32.fm - Rev. C 6/05 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
512Mb : x32 TwinDie Mobile SDRAM Addendum
Commands
AUTO REFRESH command every 7.81µs will meet the refresh requirement and ensure
that each row is refreshed. Alternatively, 8,192 AUTO REFRESH commands can be issued
in a burst at the minimum cycle rate (
t
RC), once every 64ms.
Figure 1:
Functional Block Diagram
CS
CLK
CKE#
TOP
DIE
BOTTOM
DIE
Command
Addresses
DQ0-DQ31
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512Mb Mobile SDRAM_TwinDie_x32.fm - Rev. C 6/05 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
512Mb : x32 TwinDie Mobile SDRAM Addendum
Ball Assignment
Ball Assignment
Figure 2:
90-Ball FBGA Assignment
1
A
DQ26
2
3
4
5
6
7
8
9
DQ24
V
SS
V
DD
DQ23
DQ21
B
DQ28
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
DQ19
C
V
SS
Q
DQ27
DQ25
DQ22
DQ20
V
DD
Q
D
V
SS
Q
DQ29
DQ30
DQ17
DQ18
V
DD
Q
E
V
DD
Q
DQ31
NC
NC
DQ16
V
SS
Q
F
V
SS
DQM3
A3
A2
DQM2
V
DD
G
A4
A5
A6
A10
A0
A1
H
A7
A8
A12
NC
BA1
A11
J
CLK
CKE
A9
BA0
CS#
RAS#
K
DQM1
NC
NC
CAS#
WE#
DQM0
L
V
DD
Q
DQ8
V
SS
V
DD
DQ7
V
SS
Q
M
V
SS
Q
DQ10
DQ9
DQ6
DQ5
V
DD
Q
N
V
SS
Q
DQ12
DQ14
DQ1
DQ3
V
DD
Q
P
DQ11
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
DQ4
R
DQ13
DQ15
V
SS
V
DD
DQ0
DQ2
Ball and Array
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512Mb Mobile SDRAM_TwinDie_x32.fm - Rev. C 6/05 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
512Mb : x32 TwinDie Mobile SDRAM Addendum
Electrical Specifications
Electrical Specifications
Table 3:
DC Electrical Characteristics and Operating Conditions (LC version)
V
DD
/V
DD
Q = +3.3V ±0.3V
Notes: 1, 5, 6; please refer to the 256Mb: x32 Mobile SDRAM data sheet for all notes.
Parameter/Condition
Supply Voltage
Input High Voltage: Logic 1; All inputs
Input Low Voltage: Logic 0; All inputs
Input Leakage Current:
Any input 0V
≤
V
IN
≤
V
DD
(All other balls not under test = 0V)
Output Leakage Current: DQs are disabled; 0V
≤
V
OUT
≤
V
DD
Q
Output Levels:
Symbol
MIN
3
0.8 x
V
DD
Q
-0.3
-5
MAX
3.6
Units
V
V
V
µA
Notes
22
22
V
DD
/V
DD
Q
V
IH
V
IL
I
I
V
DD
+ 0.3
0.3
5
I
OZ
V
OH
V
OL
-5
5
–
0.2
µA
V
V
V
DD
Q
- 0.2
–
Output High Voltage (I
OUT
= -4mA)
Output Low Voltage (I
OUT
= 4mA)
Table 4:
DC Electrical Characteristics and Operating Conditions (V version)
V
DD
= +2.5V ±0.2V V
DD
Q = +2.5V ±0.2V or V
DD
Q = +1.8V ±0.15V
Notes: 1, 5, 6; please refer to the 256Mb: x32 Mobile SDRAM data sheet for all notes.
Parameter/Condition
Supply Voltage
Input High Voltage: Logic 1; All inputs
Input Low Voltage: Logic 0; All inputs
Input Leakage Current:
Any input 0V
≤
V
IN
≤
V
DD
(All other balls not under test = 0V)
Output Leakage Current: DQs are disabled; 0V
≤
V
OUT
≤
V
DD
Q
Output Levels:
Symbol
MIN
2.3
0.8 x V
DD
Q
-0.3
-3.0
MAX
2.7
Units
V
V
V
µA
Notes
22
22
V
DD
/V
DD
Q
V
IH
V
IL
I
I
V
DD
Q + 0.3
0.3
3.0
I
OZ
V
OH
V
OL
-3.0
0.9 x VDDQ
–
3.0
–
0.2
µA
V
V
Output High Voltage (I
OUT
= -4mA)
Output Low Voltage (I
OUT
= 4mA)
PDF: 09005aef817f1b8c/Source: 09005aef818112f1
512Mb Mobile SDRAM_TwinDie_x32.fm - Rev. C 6/05 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
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