8M x 32 FLASH Module
PUMA 84FV256006 - 90/12/15
Issue 5.1 April 2001
Description
The PUMA 84 range of devices provide a high
density, surface mount memory solution with
density up to twice that of standard monolithic
devices.
The PUMA 84 may accomodate various memory
technologies including SRAM, FLASH and
EEPROM. The devices are designed to offer a
defined upgrade path and may be user configured
as 8, 16 or 32 bits wide.
The PUMA 84FV256006 is a 8M x 32, 3.3V FLASH
Module in a 84 ‘J’ Leaded package which complies
with the JEDEC 84 PLCC standard.
Access times of 90/120/150 ns are available.
The 3.3V device is available to commercial and
industrial temperature grade.
Block Diagram
A0 ~A21
/OE
/RESET
4M x 8
FLASH
D0 ~ 7
/CS1
/WE1
4M x 8
FLASH
D0 ~ 7
/CS5
/WE5
4M x 8
FLASH
D8 ~ 15
/CS2
/WE2
4M x 8
FLASH
D8 ~ 15
/CS6
/WE6
4M x 8
FLASH
D16 ~ 23
/CS3
/WE3
4M x 8
FLASH
D16 ~ 23
/CS7
/WE7
Features
• Access times of 90, 120 and 150ns.
• 3.3V + 10% V
CC
.
• Commercial and Industrial temperature grades
• JEDEC Standard 84 ‘J’ Lead surface mount
package.
• May be organised as 8M x 32, 16M x 16 and
32M x 8
• Flexible Sector (64 KByte) Architecture.
• Embedded Algorithms.
• Multiple Ground pins for maximum noise
immunity.
4M x 8
FLASH
D24 ~ 31
/CS4
/WE4
4M x 8
FLASH
D24 ~ 31
/CS8
/WE8
Pin Definition
See page 2.
Pin Functions
Description
Address Input
Data Input/Output
Chip Select
Write Enable
Output Enable
Hardware Reset
No Connect
Power
Ground
Signal
A0~A21
D0~D31
/CS1~8
/WE1-8
/OE
/RESET
NC
V
CC
V
SS
Package Details
PUMA 84 - Plastic 84 ‘J’ Leaded Package.
Max. Dimensions - 30.35 x 30.35 x 6.00 (nom)
All Dimensions in mm.
Package Details
PUMA 84 - Plastic 84 ‘J’ Leaded Package.
30.35 (1.195) sq.
30.10 (1.185) sq.
0.90
(0.035)
typ.
Ordering Information
1.27
(0.050) typ.
29.20 (1.150)
0.46
(0.018) typ.
Ordering Information
PUMA 84.V256006I - 90
Speed
6.00
(0.236)
max
90 = 90ns
12 = 120ns
15 = 150ns
Blank = Commercial
I = Industrial
256006 = configurable as
8M x 32, 16M x 16 or
32M x 8
V = 3.3V + 10% V
CC
F = FLASH
PUMA 84 = Plastic 84 ‘J’ Leaded
Package
Temperature Range
Memory Organisation
Power Consumption
Technology
Package
Note :
Although this data is believed to be accurate the information contained herein is not intended to and does not create
any warranty of merchantibility or fitness for a particular purpose.
Our products are subject to a constant process of development. Data may be changed without notice.
Products are not authorised for use as critical components in life support devices without the express written
approval of a company director.
PAGE 3
Issue 5.1 April 2001
28.20 (1.110)
FPGA/CPLD
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