ADVANCE
TECHNOLOGY, INC.
MT36LD872(X)
8 MEG x 72 DRAM MODULE
DRAM
MODULE
FEATURES
• JEDEC- and industry-standard ECC pinout in a 168-
pin, dual-in-line memory module (DIMM)
• High-performance CMOS silicon-gate process
• Single +3.3V
±0.3V
power supply
• All device pins are TTL-compatible
• Low power, 36mW standby; 6,480mW active, typical
• Refresh modes:
?
R
?
A
/
S ONLY,
?
C
?
A
/
S-BEFORE-?R
?
A
/
S (CBR)
and HIDDEN
• All inputs are buffered except
?
R
?
A
/
S
• 2,048-cycle refresh distributed across 32ms
• FAST PAGE MODE (FPM) operating mode or
Extended Data-Out (EDO) PAGE MODE operating
mode
• 5V-tolerant inputs and I/Os (5.5V maximum V
IH
level)
8 MEG x 72
64 MEGABYTE, ECC, 3.3V, FAST
PAGE OR EDO PAGE MODE
PIN ASSIGNMENT (Front View)
168-Pin DIMM
(DE-18)
OPTIONS
• Timing
60ns access
70ns access
• Packages
168-pin DIMM (gold)
• Operating Mode
FAST PAGE MODE
EDO PAGE MODE
MARKING
-6
-7
G
Blank
X
KEY TIMING PARAMETERS
EDO Operating Mode
SPEED
-6
-7
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
105ns
125ns
60ns
70ns
25ns
30ns
35ns
40ns
20ns
25ns
12ns
12ns
FPM Operating Mode
SPEED
-6
-7
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
RP
110ns
130ns
60ns
70ns
35ns
40ns
35ns
40ns
20ns
25ns
40ns
50ns
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
SYMBOL
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
DQ8
Vss
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ14
DQ15
DQ16
DQ17
Vss
NC
NC
Vcc
?
W
/
E
/
0
/
C
?
A
?
S
/
0
RFU
/
R
?
A
?
S
/
0
?
O
/
E
/
0
Vss
A0
A2
A4
A6
A8
A10
NC
Vcc
RFU
RFU
PIN #
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
SYMBOL
Vss
?
O
?
E
/
2
/
R
?
A
?
S
/
2
/
C
?
A
?
S
/
4
RFU
?
W
/
E
/
2
Vcc
NC
NC
DQ18
DQ19
Vss
DQ20
DQ21
DQ22
DQ23
Vcc
DQ24
RFU
RFU
RFU
RFU
DQ25
DQ26
DQ27
Vss
DQ28
DQ29
DQ30
DQ31
Vcc
DQ32
DQ33
DQ34
DQ35
Vss
PD1
PD3
PD5
PD7
ID0
Vcc
PIN #
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
SYMBOL
Vss
DQ36
DQ37
DQ38
DQ39
Vcc
DQ40
DQ41
DQ42
DQ43
DQ44
Vss
DQ45
DQ46
DQ47
DQ48
DQ49
Vcc
DQ50
DQ51
DQ52
DQ53
Vss
NC
NC
Vcc
RFU
/
CA
?
S1
? /
RFU
/
RAS
/
1
? ?
RFU
Vss
A1
A3
A5
A7
A9
NC
NC
Vcc
RFU
B0
PIN #
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
SYMBOL
Vss
RFU
/
R
?
AS
/
3
?
/
C
?
A
?
S
/
5
RFU
/
PDE
? /
Vcc
NC
NC
DQ54
DQ55
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
RFU
RFU
RFU
RFU
DQ61
DQ62
DQ63
Vss
DQ64
DQ65
DQ66
DQ67
Vcc
DQ68
DQ69
DQ70
DQ71
Vss
PD2
PD4
PD6
PD8
ID1
Vcc
MT36LD872(X)
DM62.pm5 – Rev. 12/95
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,
Micron Technology, Inc.
ADVANCE
TECHNOLOGY, INC.
MT36LD872(X)
8 MEG x 72 DRAM MODULE
occur, and the data-outputs will drive read data from the
accessed location.
PART NUMBERS
EDO Operating Mode
PART NUMBER
MT36LD872G-xx X
DESCRIPTION
8 Meg x 72, ECC, EDO, Gold
FAST PAGE MODE
FAST PAGE MODE operations allow faster data opera-
tions (READ or WRITE) within a row-address-defined
page boundary. The FAST PAGE MODE cycle is always
initiated with a row-address strobed-in by
?
R
?
A
/
S followed
by a column-address strobed-in by
?
C
?
A
/
S.
?
C
?
A
/
S may be
toggled-in by holding
?
R
?
A
/
S LOW and strobing-in different
column-addresses, thus executing faster memory cycles.
Returning
?
R
?
A
/
S HIGH terminates the FAST PAGE MODE
operation.
xx = speed
FPM Operating Mode
PART NUMBER
MT36LD872G-xx
DESCRIPTION
8 Meg x 72, ECC, FPM, Gold
xx = speed
GENERAL DESCRIPTION
The MT36LD872(X) is a randomly accessed 64MB solid-
state memory organized in a x72 configuration. It is spe-
cially processed to operate from 3.0V to 3.6V for low-volt-
age memory systems.
During READ or WRITE cycles, each bit is uniquely
addressed through the 22 address bits, which are entered 11
bits (A0 /B0-A10) at a time. Two copies of address 0 (A0 and
B0) are defined to allow maximum performance for 4-byte
applications which interleave between two 4-byte banks.
A0 is common to the DRAMs used for DQ0-DQ35, while B0
is common to the DRAMs used for DQ36-DQ71.
?
R
?
A
/
S is used
to latch the first 11 bits and
?
C
?
A
/
S the latter 11 bits.
READ and WRITE cycles are selected with the
?
W
/
E input.
A logic HIGH on
?
W
/
E dictates READ mode while a logic
LOW on
?
W
/
E dictates WRITE mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of
?
W
/
E or
?
C
?
A
/
S,
whichever occurs last. An EARLY WRITE occurs when
?
W
/
E is taken LOW prior to
?
C
?
AS falling. A LATE WRITE or
/
READ-MODIFY-WRITE occurs when
?
W
/
E falls after
?
C
?
A
/
S
was taken LOW. During EARLY WRITE cycles, the data-
outputs (Q) will remain High-Z regardless of the state of
?
O
/
E. During LATE WRITE or READ-MODIFY-WRITE cycles,
?
O
/
E must be taken HIGH to disable the data-outputs prior to
applying input data. If a LATE WRITE or READ-MODIFY-
WRITE is attempted while keeping
?
O
/
E LOW, no write will
EDO PAGE MODE
EDO PAGE MODE, designated by the “X” version, is an
accelerated FAST PAGE MODE cycle. The primary advan-
tage of EDO is the availability of data-out even after
?
C
?
A
/
S
goes back HIGH. EDO provides for
?
C
?
A
/
S precharge time
(
t
CP) to occur without the output data going invalid. This
elimination of
?
C
?
A
/
S output control provides for pipeline
READs.
FAST-PAGE-MODE modules have traditionally turned
the output buffers off (High-Z) with the rising edge of
?
C
?
A
/
S. EDO-PAGE-MODE DRAMs operate similar to FAST-
PAGE-MODE DRAMs, except data will remain valid or
become valid after
?
C
?
A
/
S goes HIGH during READs, pro-
vided
?
R
?
A
/
S and
?
O
/
E are held LOW. If
?
O
/
E is pulsed while
?
R
?
A
/
S and
?
C
?
A
/
S are LOW, data will toggle from valid data to
High-Z and back to the same valid data. If
?
O
/
E is toggled or
pulsed after
?
C
?
A
/
S goes HIGH while
?
R
?
A
/
S remains LOW, data
will transition to and remain High-Z.
During an application, if the DQ outputs are wire OR’d,
?
O
/
E must be used to disable idle banks of DRAMs. Alterna-
tively, pulsing
?
W
/
E to the idle banks during
?
C
?
A
/
S HIGH time
will also High-Z the outputs. Independent of
?
O
/
E control,
the outputs will disable after
t
OFF, which is referenced
from the rising edge of
?
R
?
A
/
S or
?
C
?
A
/
S, whichever occurs last
(reference the MT4LC4M4E8 DRAM data sheet for addi-
tional information on EDO functionality).
MT36LD872(X)
DM62.pm5 – Rev. 12/95
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,
Micron Technology, Inc.
ADVANCE
TECHNOLOGY, INC.
MT36LD872(X)
8 MEG x 72 DRAM MODULE
PIN DESCRIPTIONS
PIN NUMBERS
30, 45, 114, 129
SYMBOL
?
R
?
A
/
S
/
0 -?R
?
A
/
S
/
3
TYPE
Input
DESCRIPTION
Row-Address Strobe:
?
R
?
A
/
S is used to clock-in the 11 row-
address bits. Two
?
R
?
A
/
S inputs allow for one x72 bank or
two x36 banks.
Column-Address Strobe:
?
C
?
A
/
S is used to clock-in the 10/11
column-address bits, enable the DRAM output buffers
and strobe the data inputs on WRITE cycles.
Write Enable:
?
W
/
E is the READ/WRITE control for the DQ
pins.
?
W
/
E
/
0 controls DQ0-DQ35.
?
W
/
E
/
2 controls DQ36-
DQ71. If
?
W
/
E is LOW prior to
?
C
?
A
/
S going LOW, the access
is an EARLY WRITE cycle. If
?
W
/
E is HIGH while
?
C
?
A
/
S is
LOW, the access is a READ cycle, provided
?
O
/
E is also
LOW. If
?
W
/
E goes LOW after
?
C
?
A
/
S goes LOW, then the
cycle is a LATE WRITE cycle. A LATE WRITE cycle is
generally used in conjunction with a READ cycle to form a
READ-MODIFY-WRITE cycle.
Output Enable:
?
O
/
E is the input/output control for the DQ
pins.
?
O
/
E
/
0 controls DQ0-DQ35.
?
O
/
E
/
2 controls DQ36-DQ71.
These signals may be driven, allowing LATE WRITE
cycles.
Address Inputs: These inputs are multiplexed and clocked
by
?
R
?
A
/
S and
?
C
?
A
/
S. A0 is common to the DRAMs used for
DQ0-DQ35 while B0 is common to the DRAMs used for
DQ36-DQ71
Data I/O: For WRITE cycles, DQ0-DQ71 act as inputs to
the addressed DRAM location. For READ access cycles,
DQ0-DQ71 act as outputs for the addressed DRAM
location.
28, 46, 112, 130
?
CA
/
S
/
0, C
?
A
/
S
/
4
?
?
/
C
?
A
/
S
/
1,
/
C
?
A
/
S
/
5
?
W
/
E
/
0,
?
W
/
E
/
2
Buffered Input
27, 48
Buffered Input
31, 44
?
OE
/
0, OE
/
2
/
? /
Buffered Input
33-38, 117-121, 126
A0-A10, B0
Buffered Input
2-5, 7-11, 13-17, 19-22,
52-53, 55-58, 60, 65-67,
69-72, 74-77, 86-89,
91-95, 97-101, 103-106,
136-137, 139-142,
144, 149-151, 153-156,
158-161
79-82, 163-166
DQ0-DQ71
Input/
Output
PD1-PD8
Buffered
Output
—
Presence-Detect: These pins are read by the host system
and tell the system the DIMM’s personality. They will be
either driven to V
OH
(1) or they will be driven to V
OL
(0).
RFU: These pins should be left unconnected
(reserved for future use).
Power Supply: +3.3V
±
0.3V
29, 41-42, 47, 61-64, 111,
113, 115, 125, 128, 131,
145-148
6, 18, 26, 40, 49, 59, 73,
84, 90, 102, 110, 124,
133, 143, 157, 168
RFU
V
CC
Supply
MT36LD872(X)
DM62.pm5 – Rev. 12/95
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,
Micron Technology, Inc.
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