REVISIONS
LTR
A
DESCRIPTION
Added case outline U, and updated associated paragraphs and
figures. Added note 6 to section 1.3 and renumbered existing.
Updated lead solder temperature in section 1.3. Added note to
section 1.6.3. Updated figure in Table I footnote 10. ksr
Add device types 05 through 08 to section 1.2.2; add and edit footnote
designations in section 1.2.2 and the corresponding footnotes at
bottom of page 2. Made additional changes in paragraphs for
inclusion of devices 05 through 08 where applicable. Added new test
in 4.4.1.f.(4) for thermal runaway. Made changes to Table I where
applicable, also corrected figure in footnote 6/ of
Table I. ksr
Change maximum Input voltage (V
I
) in section 1.3 from 3.75 V to 4.1
V max, change Maximum junction temperature (T
J
) from 125
o
C to
135
o
C, and update footnote 10/. Make changes to Table I;
clarifications for 5 V tolerance, standby currents, and I/O related
changes. Edit notes 2, 3, and 8 on Figure 2; and add note 10. ksr
DATE (YR-MO-DA)
07-04-23
APPROVED
Robert M. Heber
B
08-03-12
Robert M. Heber
C
09-08-17
Charles F. Saffle
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
C
35
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36
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18
REV
SHEET
PREPARED BY
Kenneth Rice
CHECKED BY
Rajesh Pithadia
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DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
http://www.dscc.dla.mil
APPROVED BY
Raymond Monnin
DRAWING APPROVAL DATE
06-04-20
REVISION LEVEL
C
MICROCIRCUIT, MEMORY, DIGITAL,
CMOS, FIELD PROGRAMMABLE GATE
ARRAY,
1,000,000
GATES,
MONOLITHIC SILICON
SIZE
CAGE CODE
A
SHEET
67268
1 OF
36
5962-04220
5962-E407-09
DSCC FORM 2233
APR 97
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and
M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the
Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the
PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
|
|
|
Federal
stock class
designator
\
-
|
|
|
RHA
designator
(see 1.2.1)
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and
are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number
Circuit function
01
RTAX1000S
1,000,000 gate field programmable gate array
02
RTAX1000S-1
1,000,000 gate field programmable gate array
1/
03
RTAX1000S
1,000,000 gate field programmable gate array
2/
04
RTAX1000S-1
1,000,000 gate field programmable gate array
1/ 3/
05
RTAX1000SL
1,000,000 gate field programmable gate array
4/
06
RTAX1000SL-1
1,000,000 gate field programmable gate array
1/ 4/
07
RTAX1000SL
1,000,000 gate field programmable gate array
4/ 5/
08
RTAX1000SL-1
1,000,000 gate field programmable gate array
1/ 4/ 6/
Note: These devices are specified at junction operating temperature and not at case operating temperature.
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
Device requirements documentation
M
Q or V
Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN
class level B microcircuits in accordance with MIL-PRF-38535, appendix A
Certification and qualification to MIL-PRF-38535
04220
01
|
|
|
Device
type
(see 1.2.2)
/
Q
|
|
|
Device
class
designator
(see 1.2.3)
X
|
|
|
Case
outline
(see 1.2.4)
C
|
|
|
Lead
finish
(see 1.2.5)
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Descriptive designator
Terminals
Package style
Outline letter
X
Y
Z
U
1/
See figure 1
See figure 1
See figure 1
See figure 1
352
624
624
624
Ceramic Quad Flat Pack
Ceramic Land Grid Array (LGA)
Ceramic Column Grid Array (CGA) 7/
Ceramic Column Grid Array (CGA) 7/
2/
3/
4/
5/
6/
7/
Timing performance of the RTAX1000S-1 and RTAX1000SL-1 devices shall be approximately 15% faster than the
RTAX1000S and RTAX1000SL devices respectively (End users may select the appropriate device speed grade through
timing calculations based on timing simulation of specific designs with manufacturer's Libero/Designer software, see 6.7
herein).
Device type 03 is device type 01 with additional testing (see 4.2.2.f).
Device type 04 is device type 02 with additional testing (see 4.2.2.f).
Silicon used for all devices are the same silicon, at 125
o
C final electrical test, device type 05 to 08 is screened to a lower
I
CCA
limit (see Table I herein)
Device type 07 is device type 05 with additional testing (see 4.2.2.f).
Device type 08 is device type 06 with additional testing (see 4.2.2.f).
Case outline U has a different solder composition than Z(see Figure 1 for details).
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
5962-04220
SHEET
C
2
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
1.3 Absolute maximum ratings (for 1.5V/1.8V/2.5V/3.3V operating conditions). 8/
DC core supply voltage (V
CCA
) ............................................................... -0.3 to +1.7 V
DC I/O supply voltage (V
CCI
) ................................................................... -0.3 to +3.75 V
DC supply voltage for differential I/Os (V
CCDA
) ....................................... -0.3 to +3.75 V
DC I/O reference voltage (V
REF
) ............................................................. -0.3 to +3.75 V
DC external pump supply voltage (V
PUMP
) ............................................. -0.3 to +3.75 V
Input voltage (V
I
) ..................................................................................... -0.5 to +4.1 V 9/
Output voltage (V
O
) ................................................................................. -0.5 to +3.75 V
Storage temperature range (V
STG
) ......................................................... -65
o
C to +150
o
C
o
Lead temperature (soldering, 10 seconds) X ............................................ 300 C
Y, Z, and U ........................... 245C
Maximum junction temperature (T
J
) ........................................................ 135
o
C
10/
Thermal resistance, junction-to-case (
JC
):
Case outline X ...................................................................................... 0.4
o
C/W 11/ 14/
Case outline Y ...................................................................................... 5.7
o
C/W 12/ 14/
Case outlines Z and U ........................................................................... 5.6
o
C/W 12/ 14/
Thermal resistance, junction-to-board (
JB
) for case outline Z and U....... 4.5
o
C/W 13/ 14/
AC core supply transient voltage (V
CCA
) .................................................. -0.3 to +1.8 V 15/
1.4 Recommended operating conditions.
1.5V core supply voltage ........................................................................................... 1.425 to 1.575 V dc
1.5V I/O supply voltage .............................................................................................. 1.425 to 1.575 V dc
1.8V I/O supply voltage .............................................................................................. 1.71 to 1.89 V dc
2.5V I/O supply voltage .............................................................................................. 2.375 to 2.625 V dc
3.3V I/O supply voltage .............................................................................................. 3.0 to 3.6 V dc
2.5V V
CCDA
I/O supply voltage (no differential I/O used) .......................................... 2.375 to 2.625 V dc
3.3V V
CCDA
I/O supply voltage (differential or voltage referenced I/O used) ............ 3.0 to 3.6 V dc
3.3V V
PUMP
supply voltage range ............................................................................. 3.0 to 3.6 V dc
Junction operating temperature range (T
J
) ................................................................ -55
o
C to +125
o
C
8/
9/
Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
Overshoot/Undershoot limits: For AC signals, the input signal may undershoot during transitions to -1.0 V for no longer
than 10% of the period or 11 ns whichever is smaller. Current during the transition must not exceed 95 mA. For AC
signals, the input signal may overshoot during transitions to V
CCI
+ 1.0 V for no longer than 10% of the period or 11 ns
whichever is smaller. Current during the transition must not exceed 95 mA. Note: This specification does not apply to the
PCI standard. The PCI I/Os of this device are compliant to the PCI standard including the PCI overshoot/undershoot
specifications.
Maximum junction temperature shall not be exceeded except for allowable short durations during burn-in screening
conditions in accordance with method 5004 of MIL-STD-883. Tj=135
o
C applies with wafer lot numbers starting with
D2xxxx. For older wafer lot numbers starting with D1xxxx , the Tj=125
o
C still applies.
JC
for case outline X refers to the thermal resistance between the junction and the bottom of the package.
JC
for case outlines Y, Z, and U refers to the thermal resistance between the junction and the top of the package (surface
of the metal lid).
JB
for case outlines Z and U refers to the thermal resistance between the junction and the tips of the solder columns
(where the device is attached to the circuit board)
All thermal resistance data are obtained through simulation with computational fluid dynamic software. For case outlines Z
and U, the
JB
is simulated with 4L/2P SMT board per JESD51.
AC transient V
CCA
limit is for radiation induced transients less than 10s duration, and not intended for repetitive use. Core
voltage spikes from a single event transient will not negatively affect the reliability of the device if, for this non-repetitive
event, the transient does not exceed 1.8 V at any time, and the total time that the transient exceeds 1.575 V does not
exceed 10
s
in duration.
10/
11/
12/
13/
14/
15/
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
5962-04220
SHEET
C
3
1.5 Power-Up/Down Sequence. All device I/Os are tri-stated during power-up until normal device operating conditions are
reached, which is when I/Os enter user mode. V
CCA
, V
CCI
, and V
CCDA
can be powered up or powered down in any
sequence. All device I/Os are hot-swap compliant with cold-sparing support (except PCI).
1.5.1 R-cells and I/O Registers. On a chip-wide basis at power-up, all R-cells and I/O Registers are either cleared or preset
by driving the global clear (GCLR) and global preset (GPSET) inputs (see Figure 3). Default setting is to clear all registers
(GCLR = 0 and GPSET =1) at device power-up.
1.6 Device Logic Configuration.
1.6.1 Core array logics include two types of logic modules: the register cell (R-cell) and the combinatorial cell (C-cell). C-cell
contains carry logic for efficient arithmetic functions. R-cell appears as a single D-type flip-flop to user, but is implemented in
silicon with triple module redundancy (TMR) to improve SEU performance. Each TMR R-cell consist of three master-slave
latch pairs, each with asynchronous self-correcting feedback paths. Output of the TMR R-cell is the result of the majority voting
of the outputs of the three flip flops in the TMR R-cells. Logic modules are grouped as SuperCluster, each SuperCluster has
two Clusters, and each Cluster includes two C-cells, one R-cell, two transmit (TX) and two receive (RX) routing buffers. Each
SuperCluster also includes an independent buffer module. On the chip level, SuperClusters are organized into core tiles, which
are arrayed to build up the full chip. There are nine core tiles in this device and each tile has 336 SuperClusters, resulting a
total of 6,048 R-cells and 12,096 C-cells in the device.
1.6.2 Clock Resources are available with two types of global clock networks throughout the chip. There are four dedicated
hardwired clock input pins (HCLKA/B/C/D) that will directly drive all the sequential modules (R-cells, I/O registers, embedded
RAM/FIFO). There are also four global clock input pins (CLKE/F/G/H) for routed clock distribution networks that are buffered
prior to clocking the R-cells; the routed clocks can also be programmed to drive S0, S1, PSET, and CLR of a register, or as the
inputs of any C-cell. Input levels for all clocks are compatible with all supported I/O standards (there is a P/N pin pair to
support differential I/O standards). All clock networks have been hardened to improve SEU performance.
1.6.3 Embedded RAM is available as a global resource. There are four 4,608-bit RAM blocks in each tile, with a total of
165,888 bits in the device. Each 4,608-bit RAM block can be organized as 128x36, 256x18, 512x9, 1,024x4, 2,048x2, or 4,096
x1 (Depth x Word in bits), and are cascadable to create larger memory sizes. Each RAM block has independent read and write
ports, which enables simultaneous read and write operations; it also contains its own embedded FIFO controller, allowing the
RAM blocks to be configured as either RAM or FIFO. SRAM structures are susceptible to radiation upsets, to achieve high
level SEU performance, manufacturer has provided an IP core to enhance the SEU tolerance of the embedded RAM blocks by
mitigating upsets with Error Detection and Correction (EDAC) and background memory-refresher (or scrubber). Registers in
the FIFO controller are not hardened for radiation, so when high SEU tolerance is required, the FIFO control unit should be
implemented with core logic. Note: Simultaneous read and write operations to the same address is not supported.
1.6.4 Multi-Standard I/Os are available on all I/O pins. Below table shows all supported I/O standards.
I/O Standard
LVTTL
LVCMOS 2.5V
LVCMOS 1.8V
LVCMOS 1.5V
3.3V PCI
GTL+ 3.3V
HSTL Class I
SSTL3 Class I and II
SSTL2 Class I and II
LVDS
LVPECL
Input/Output Supply
Voltage (V
CCI
)
3.3
2.5
1.8
1.5
3.3
3.3
1.5
3.3
2.5
2.5
3.3
Input Reference
Voltage (V
REF
)
N/A
N/A
N/A
N/A
N/A
1.0
0.75
1.5
1.25
N/A
N/A
Board Termination
Voltage (V
TT
)
N/A
N/A
N/A
N/A
N/A
1.2
0.75
1.5
1.25
N/A
N/A
Each I/O
provides
programmable slew rates, drive strength, and weak pull-up and pull-down circuits (in the order of 10k), it also includes three
registers (input (InReg), output (OutReg), and enable (EnReg)). I/Os are organized into eight banks (0-7) with two banks per
device side. Each I/O bank has a common V
CCI
and a common reference-voltage bus. For each I/O bank, multiple I/O
standards may be selected, however, all I/O standards used in the same I/O bank shall have the same V
CCI
value and the
same V
REF
value (when required). V
REF
pin is not pre-defined, any user I/O in the bank can be selected to be a V
REF
.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
5962-04220
SHEET
C
4
1.6.5 Routing Resource provides hierarchical routing structure that ties the logic modules, the embedded memory block,
and the I/O modules together. User designs can be implemented with manufacturer’s Designer software (see 6.7 herein),
which includes a Timer that supports timing-driven place-and-route; plus SmartPower for power estimation; PinEditor and I/O
Attribute Editor for I/O assignments and I/O attributes; Netlist Viewer and ChipPlanner for design implementation. Additionally,
Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single
environment (see 6.7 herein).
1.6.6 Calculation for Junction Temperature. The temperature variable in the manufacturer’s Designer software refers to the
junction temperature, not the ambient, case, or board temperature. The operating temperature at case (T
C
) can be calculated
with
JC
=
(
T
J
– T
C
)
P; and the operating temperature at board interface (T
B
) for case outline Z can be calculated with
JB
=
(
T
J
– T
B
)
P. P is the device power consumption, which differs among user designs. Power usage can be determined by
logic cell utilization; clock usage and frequency; input cell utilization and frequency; output cell utilization, V
CCI
level and output
frequency; and static power consumption. The manufacturer’s software tool will assist users on power estimation.
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in
the solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 -
MIL-STD-1835 -
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 -
MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at
http://assist.daps.dla.mil/quicksearch/
or from the Standardization
Document Order Desk, 700 Robins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation.
AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM)
ASTM Standard F1192
Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by
Heavy Ion Irradiation of Semiconductor Devices.
(Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr Harbor
Drive, West Conshohocken, PA 19428-2959;
http://www.astm.org.)
ELECTRONICS INDUSTRIES ASSOCIATION (EIA)
JEDEC Standard EIA/JESD51 -
JEDEC Standard EIA/JESD78 -
ANSI/TIA/EIA Standard EIA-644 -
J-STD-002
High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
IC Latch-Up Test.
Electrical Characteristics of Low-Voltage Differential Signaling (LVDS) Interface
Circuits
Solderability Tests for Component Leads, Terminations, Lugs, Terminals and Wires
(Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA
22201;
http://www.jedec.org.)
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
5962-04220
SHEET
C
5
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