QS5925
PROGRAMMABLE FREQUENCY GENERATOR
INDUSTRIAL TEMPERATURE RANGE
PROGRAMMABLE
FREQUENCY GENERATOR
QS5925
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
4 programmable frequency outputs
Optional crystal input, internal capacitors
Balanced Drive Outputs ±12mA
PLL disable mode for low frequency testing
Tri-state output enable (OE)
PHY/MAC networking applications
Input frequencies up to 80MHz
Output frequencies up to 160MHz
5V tolerant inputs
Low output skew/jitter
External feedback, internal loop filter
3V to 3.6V supply voltage
Available in 16-pin QSOP package
DESCRIPTION:
The QS5925 is a high-performance, low skew, low jitter phase-locked
loop (PLL) clock driver. It provides precise phase and frequency alignment
of its clock outputs to an externally applied clock input or internal crystal
oscillator. The QS5925 has been specially designed to interface with
Gigabit Ethernet and Fast Ethernet applications by providing a 125MHz
clock from 25MHz input. It can also be programmed to provide output
frequencies ranging from 3.125MHz to 160MHz with input frequencies
ranging from 3.125MHz to 80MHz. The QS5925 includes an internal RC
filter that provides excellent jitter characteristics and eliminates the need for
external components. When using the optional crystal input, the X
2
pin must
be connected to the CLKIN pin. The on-chip crystal oscillator includes the
feedback resistor and crystal capacitors (nominal load capacitance is
15pF), and requires a fundamental mode crystal with a maximum equiva-
lent series resistance of 50Ω.
FUNCTIONAL BLOCK DIAGRAM
S
0
S
1
SELEC T
M OD E
FB
CLKIN
PH A SE
DETECTO R
LO O P
FILTER
VCO
0
FREQ UEN CY
DIVIDER
Q /N
1/N
Q
0
1
X
2
XTAL
X
1
O PTIO NA L
CR YSTAL
O SC
Q
1
Q
2
OE
INDUSTRIAL TEMPERATURE RANGE
1
c
2001 Integrated Device Technology, Inc.
JANUARY 2001
DSC-5776/2
QS5925
PROGRAMMABLE FREQUENCY GENERATOR
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
S
1
S
0
G NDQ
V
DD Q
X
1
X
2
CLKIN
FB
1
2
3
4
5
6
7
8
QSOP
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
Symbol
V
TERM
Description
Supply Voltage to Ground
DC Output Voltage V
OUT
DC Input Voltage V
IN
T
A
= 85°C
Maximum Power Dissipation
Storage Temperature
T
STG
Max.
– 0.5 to +7
– 0.5 to Vcc +0.5
– 0.5 to +7
.55
– 65 to +150
(1)
Unit
V
V
V
W
°C
16
15
14
SO 16-7
13
12
11
10
9
V
D DN
G NDN
Q
2
Q
1
Q
0
Q /N
G NDN
OE
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
PIN DESCRIPTION
Pin Names
CLKIN
X
1
(1)
X
2
(1)
FB
QTY
1
1
1
1
I/O
I
I
O
I
Description
Input clock
Crystal oscillator input
Crystal oscillator output
PLL feedback input which should be
connected to Q/N output pin only. PLL
locks onto +ve edge of FB signal.
Mode/Frequency select inputs (three-level)
Clock outputs
Programmable divide-by-N clock output
Tri-state output enable. When asserted
HIGH, clock outputs are high impedance.
Power supply for output buffers
Ground supply for output buffers
Power supply for PLL
Ground supply for PLL
Sx
Qx
Q/N
OE
V
DDN
GNDN
V
DDQ
GNDQ
2
3
1
1
1
2
1
1
I
O
O
I
I
I
I
I
NOTE:
1. For best accuracy, use parallel resonant crystal specified for a load
capacitance of 15pF.
FUNCTION TABLE
Output Used for
Feedback
Q/N
Allowable CLKIN Range (MHz)
(1,2)
Minimum
25/N
Maximum
160/N
Output Frequency Relationships
Q/N
CLKIN
Qx
CLKIN x N
NOTES:
1. Operation in the specified CLKIN frequency range guarantees that the VCO will operate in the optimal range of 25MHz to 160MHz. Operation with
CLKIN outside specified frequency ranges may result in invalid or out-of-lock outputs.
2. Qx is not allowed to be used as feedback.
2
QS5925
PROGRAMMABLE FREQUENCY GENERATOR
INDUSTRIAL TEMPERATURE RANGE
DIVIDE SELECTION TABLE
(1)
S1
L
L
L
M
M
M
H
H
H
S0
L
M
H
L
M
H
L
M
H
2
3
4
5
(3)
6
7
8
16
Divide-by-N Value
FACTORY TEST
(2)
PLL
PLL
PLL
PLL
PLL
PLL
PLL
TEST
(4)
Mode
NOTES:
1. H = HIGH
M = MEDIUM
L = LOW
2. Factory test mode: operation not specified.
3. Ethernet mode (use a 25MHz input frequency and Q/N as feedback).
4. Test mode for low frequency testing. In this mode, CLKIN bypasses the VCO (VCO powered down). Frequency must be > 1MHz due to dynamic
circuits in the frequency dividers. Q
0
: Q
2
outputs are divided by 2 in test mode.
OPERATING CONDITIONS
Symbol
V
DD
T
A
C
L
C
IN
Parameter
Power Supply Voltage
Operating Temperature
Output Load Capacitance
Input Capacitance, CLKIN, FB,
OE,
F = 1MHz, V
IN
= 0V, T
A
= 25°C
Min
3
–40
—
—
Typ
3.3
25
—
5
Max
3.6
85
15
7
Unit
V
°C
pF
pF
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= -40°C to +85°C, V
CC
= 3.3V ± 0.3V
Symbol
V
IH
V
IHH (1)
V
IL
V
ILL (1)
V
IMM (1)
I
IH
I
IHH
I
IL
I
ILL
I
IMM
V
OH
V
OL
Input MID Current
Output HIGH Voltage
Output LOW Voltage
Input LOW Current
Input MID Voltage
Input HIGH Current
Input LOW Voltage
Parameter
Input HIGH Voltage
Test Conditions
CLKIN, FB and
OE
Sx
CLKIN, FB and
OE
Sx
Sx
V
IN
= V
DD
; CLKIN, FB and
OE
V
IN
= V
DD
; Sx
V
IN
= 0V; CLKIN, FB and
OE
V
IN
= 0V; Sx
V
IN
= V
DD
/2; Sx
V
DD
= 3V, I
OH
= -12mA
V
DD
= 3V, I
OH
= -100µA
V
DD
= 3V, I
OL
= 12mA
V
DD
= 3V, I
OL
= 100µA
Min.
2
V
DD
- 0.6
—
—
V
DD
/2 - 0.3
-5
—
-5
- 150
- 50
2.4
2.8
—
—
Typ.
—
—
—
—
—
0.07
50
—
- 50
0
2.8
—
0.15
—
Max.
—
—
0.8
0.6
V
DD
/2 + 0.3
5
150
5
—
50
—
—
0.55
0.2
V
µA
V
µA
V
µA
V
Unit
V
NOTE:
1. These inputs are normally wired to Vcc, GND, or unconnected. If the inputs are switched in real time, the function and timing of the outputs may
glitch, and the PLL may require an additional lock time before all datasheet limits are achieved.
3
QS5925
PROGRAMMABLE FREQUENCY GENERATOR
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
I
DDQ
Parameter
Quiescent Supply Current
Test Conditions
(1)
V
DD
= Max.
CLK = FB = X
1
= GND
Sx = H
OE
= H
All outputs unloaded
V
DD
= Max., V
IN
= 3V
V
DD
= 3.6V
S
0
= MID; S
1
= GND
OE
= GND
F
OUT
= 60MHz
All outputs unloaded
Min.
—
Typ.
0.7
Max
2
Unit
mA
∆I
DD
I
DD
Supply Current per Input
Dynamic Supply Current
—
—
1
77
30
130
µA
mA
NOTE:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= -40°C to +85°C, V
CC
= 3.3V ± 0.3V
Symbol
t
R
t
F
d
T
t
PD
t
SK
t
J
d
T_INPUT
t
R_INPUT
t
F_INPUT
f
OSC
f
OUT
f
IN
Parameter
Rise Time
(1)
Fall Time
(1)
Duty Cycle
(1)
CLKIN to FB Propagation Delay
(1)
Skew (output - output)
(1)
Cycle - Cycle Jitter
(1)
CLKIN Duty Cycle
(1)
CLKIN Rise Time
(1)
CLKIN Fall Time
(1)
Oscillator Frequency
Output Frequency
Input Frequency
0.8V to 2V
2V to 0.8V
V
T
= V
DD
/2
V
T
= V
DD
/2
V
T
= V
DD
/2; Qx
V
T
= V
DD
/2; Q/N - Qx
For N = 2 at 125MHz output (Qx)
V
T
= 1.5V
0.8V to 2V
0.8V to 2V
—
—
Q/N used for feedback
Test Conditions
Min.
—
—
45
- 1.6
—
—
—
25
—
—
—
25
25/N
Typ.
0.7
0.7
50
- 0.95
—
—
—
—
—
—
—
—
—
Max.
1.5
1.5
55
- 0.5
300
600
200
75
2
2
30
160
160/N
ps
%
ns
ns
MHz
MHz
MHz
Unit
ns
ns
%
ns
ps
NOTE:
1. This parameter is guaranteed by design but not tested.
4
QS5925
PROGRAMMABLE FREQUENCY GENERATOR
INDUSTRIAL TEMPERATURE RANGE
TEST LOADS AND WAVEFORMS
3V
V
CC
2V
V
T H
= V
C C
/2
150
Ω
0.8
0V
OUTPUT
1ns
1ns
Input Test Waveform
15pF
150
Ω
V
C C
2V
AC Test Load
V
T H
= V
C C
/2
0.8
0V
t
R
t
F
Output Waveform
HOW TO USE THE QS5925
The QS5925 is a general-purpose phase-locked loop (PLL) that can be
used as a zero delay buffer or a clock multiplier. It generates three outputs
at the VCO frequency and one output at the VCO frequency divided by n,
where n is determined by the Mode/Frequency Select input pins S
0
and S
1
.
The PLL will adjust the VCO frequency (within the limits of the Function
Table) to ensure that the input frequency equals the Q/N frequency.
The QS5925 can accept two types of input signal. The first is a reference
clock generated by another device on the board which needs to be
reproduced with a minimal delay between the incoming clock and output.
The second is an external crystal. When used in the first mode, the crystal
input (X
1
) should be tied to ground and the crystal output (X
2
) should be left
unconnected.
By connecting Q/N to FB (see Figure 1), the QS5925 not only becomes
a zero delay buffer, but also a clock multiplier. With proper selection of S
0
and S
1
, the Q
0
–Q
2
outputs will generate two, three, up to eight times the input
clock frequency. When used in this mode, you must make sure that the input
and output frequency specifications are not violated (refer to Function
Table). There are some applications where higher fan-out is required.
These kinds of applications could be addressed by using the QS5925 in
conjunction with a clock buffer such as the QS53805 . Figure 2 shows how
higher fan-out with different clock rates can be generated.
FB
Q /N
CLKIN
X
2
X
1
Q S5925
Q
0
Q
1
Q
2
FB
Q/N
C LKIN
QS5 925
X
2
X
1
QX
INA
5 C OP IES
OF Q/N
QS5 380 5
5 C OP IES
OF Q
INB
S
0
S
1
S
0
S
1
Figure 1
5
Figure 2
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