02 | Keysight | HMMC-3124 DC-12 GHz Packaged High Efficiency Divide-by-4 Prescaler – Data Sheet
Description
The Keysight Technologies, Inc. HMMC-3124 is a packaged GaAs HBT MMIC pre-scaler
which offers dc to 12 GHz frequency translation for use in communications and EW
systems incorporating high-frequency PLL oscillator circuits and signal-path down
conversion applications. The prescaler provides a large input power sensitivity window
and low phase noise.
Absolute maximum ratings1
(@ T
A
= 25 °C, unless otherwise indicated)
Symbol
V
CC
V
EE
V
CC
-V
EE
V
Logic
P
in (CW)
V
RFin
T
BS2
T
st
T
max
Parameters/conditions
Bias supply voltage
Bias supply voltage
Bias supply delta
Logic threshold voltage
CW RF input power
DC input voltage (@ RF
in
or RF
in
ports)
Backside ambient temperature
Storage temperature
Max. assembly temperature (60 s max.)
–40
–65
V
CC
-1.5
–7
+7
V
CC
-1.2
+10
V
CC
±0.5
+85
+165
310
Min
Max
+7
Units
volts
volts
volts
volts
dBm
volts
ºC
ºC
ºC
Package type:
8-lead SSOP plastic
Package dimensions:
4.9 x 3.9 mm typ.
Package thickness:
1.55 mm typ.
Lead pitch:
1.25 mm nom.
Lead width:
0.42 mm nom.
1. Operation in excess of any parameter limit (except T
BS
) may cause permanent damage to the device.
2. MTTF > 1 x 10
6
hours @ T
BS
≤ 85 °C. Operation in excess of maximum operating temperature (T
BS
)
will degrade MTTF.
DC specifications/physical properties
1
(T
A
= 25°C, V
CC
– V
EE
= 5.0 volts, unless otherwise listed)
Symbol
V
CC
– V
EE
| I
CC
| or | I
EE
|
Parameters/conditions
Operating bias supply difference
1
Bias supply current
Min
4.5
34
Typ
5.0
40
V
CC
V
CC
–1.45
V
CC
–1.35
V
CC
–1.25
Max
6.5
46
Units
Volts
mA
Volts
Volts
V
RFin(q),
V
RFout(q)
Quiescent dc voltage appearing at all RF ports
V
Logic
1.
Nominal ECL logic level (V
Logic
contact self-bias voltage, generated on-chip)
Prescaler will operate over full specified supply voltage range, V
CC
or V
EE
not to exceed limits specified in
Absolute maximum ratings
section.
03 | Keysight | HMMC-3124 DC-12 GHz Packaged High Efficiency Divide-by-4 Prescaler – Data Sheet
RF specifications
(T
A
= 25 °C, Z
o
= 50 Ω, V
CC
- V
EE
= 5.0 volts)
Symbol
ƒ
in(max)
ƒ
in(min)
ƒ
Self-Osc.
Parameters/conditions
Maximum input frequency of operation
Minimum input frequency of operation
1
(P
in
= −10 dBm)
Output self-oscillation frequency
2
@ dc (Square-wave input)
@ ƒ
in
= 500 MHz (Sine-wave input)
P
in
ƒ
in
= 1 to 8 GHz
ƒ
in
= 8 to 10 GHz
ƒ
in
= 10 to 12 GHz
RL
S
12
φN
Jitter
T
r
or T
f
Small-signal input/output return loss (@ ƒ
in
< 10 GHz)
Small-signal reverse isolation (@ ƒ
in
< 10 GHz)
SSB phase noise (@ P
in
= 0 dBm, 100 kHz offset from a ƒ
out
= 1.2 GHz carrier)
Input signal time variation @ zero-crossing (ƒ
in
= 10 GHz, P
in
= −10 dBm)
Output transition time (10% to 90% rise/fall time)
@ ƒ
out
< 1 GHz
P
out 3
@ ƒ
out
= 2.5 GHz
@ ƒ
out
= 3.0 GHz
@ ƒ
out
< 1 GHz
|V
out(p-p)
|
4
@ ƒ
out
= 2.5 GHz
@ ƒ
out
= 3.0 GHz
P
Spitback
P
feedthru
H
2
ƒ
out
power level appearing at RF
in
or RF
in
(@ ƒ
in
10 GHz, unused RF
out
or RF
out
unterminated)
ƒ
out
power level appearing at RF
in
or RF
in
(@ ƒ
in
= 10 GHz, both RF
out
and RF
out
terminated)
Power level of ƒ
in
appearing at RF
out
or RF
out
(@ ƒ
in
= 12 GHz, P
in
= 0 dBm, referred to
P
in
(ƒ
in
))
Second harmonic distortion output level (@ ƒ
out
= 3.0 GHz, referred to P
out
(ƒ
out
))
–2
–3.5
–4.5
−15
−15
−15
−10
−5
Min
16
Typ
18
0.2
3.4
> −25
> −20
> −20
> −15
> −10
15
30
−153
1
70
0
–1.5
–2.5
0.5
0.42
0.37
−50
−55
−30
−25
+10
+10
+10
+5
+1
0.5
Max
Units
GHz
GHz
GHz
dBm
dBm
dBm
dBm
dBm
dB
dB
dBc/Hz
ps
ps
dBm
dBm
dBm
Volts
Volts
Volts
dBm
dBm
dBc
dBc
1. For sine-wave input signal. Prescaler will operate down to D.C. for square-wave input signal. Minimum divide frequency limited by input slew-rate.
2. Prescaler may exhibit this output signal under bias in the absence of an RF input signal. This condition may be eliminated by use of the Input dc offset technique
described on page 4.
3. Fundamental of output square wave’s Fourier Series.
4. Square wave amplitude calculated from P
out
.
04 | Keysight | HMMC-3124 DC-12 GHz Packaged High Efficiency Divide-by-4 Prescaler – Data Sheet
Applications
The HMMC-3124 is designed for use in high frequency communications, microwave
instrumentation, and EW radar systems where low phase-noise PLL control circuitry or
broad-band frequency translation is required.
Operation
The device is designed to operate when driven with either a single-ended or differential
sinusoidal input signal over a 200 MHz to 12 GHz bandwidth. Below 200 MHz the
prescaler input is “slew-rate” limited, requiring fast rising and falling edge speeds to
properly divide. The device will operate at frequencies down to dc when driven with a
square-wave.
Due to the presence of an off-chip RF-bypass capacitor inside the package (connected
to the VCC contact on the device), and the unique design of the device itself, the
component may be biased from either a single positive or single negative supply bias.
The backside of the package is not dc connected to any dc bias point on the device.
For positive supply operation, VCC pins are nominally biased at any voltage in the +4.5
to +6.5 volt range with pin 8 (VEE) grounded. For negative bias operation VCC pins are
typically grounded and a negative voltage between -4.5 to -6.5 volts is applied to pin 8
(VEE).
ac-Coupling and dc-Blocking
All RF ports are dc connected on-chip to the V
CC
contact through on-chip 50 Ω resistors.
Under any bias conditions where V
CC
is not dc grounded the RF ports should be ac
coupled via series capacitors mounted on the PC-board at each RF port. Only under bias
conditions where V
CC
is dc grounded (as is typical for negative bias supply operation)
may the RF ports be direct coupled to adjacent circuitry or in some cases, such as level
shifting to subsequent stages. In the latter case the package heat sink may be “floated”
and bias applied as the difference between V
CC
and V
EE
.
Figure 1. Simplified schematic diagram
05 | Keysight | HMMC-3124 DC-12 GHz Packaged High Efficiency Divide-by-4 Prescaler – Data Sheet
Input dc Offset
If an RF signal with sufficient signal to noise ratio is present at the RF input lead, the
prescaler will operate and provide a divided output equal the input frequency divided
by the divide modulus. Under certain “ideal” conditions where the input is well matched
at the right input frequency, the component may “self-oscillate”, especially under small
signal input powers or with only noise present at the input This “self-oscillation” will
produce a undesired output signal also known as a false trigger. To prevent false triggers
or self-oscillation conditions, apply a 20 to 100 mV dc offset voltage between the RF
in
and RF
in
ports. This prevents noise or spurious low level signals from triggering the
divider.
Adding a 10 kΩ resistor between the unused RF input to a contact point at the V
EE
potential will result in an offset of ≈ 25 mV between the RF inputs. Note however, that
the input sensitivity will be reduced slightly due to the presence of this offset.
Assembly Notes
Independent of the bias applied to the package, the backside of the package should
always be connected to both a good RF ground plane and a good thermal heat sinking
region on the PC board to optimize performance. For single-ended output operation
the unused RF output lead should be terminated into 50 Ω to a contact point at the VCC
potential or to RF ground through a dc blocking capacitor.
A minimum RF and thermal PC board contact area equal to or greater than 2.67 ×
1.65 mm (0.105” × 0.065”) with eight 0.020” diameter plated-wall thermal vias is
recommended.
MMIC ESD precautions, handling considerations, die attach and bonding methods are
critical factors in successful GaAs MMIC performance and reliability.
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