19-3855; Rev 1; 4/06
2-/4-/6-/8-Channel, ±30kV ESD Protectors in µDFN
General Description
The MAX13202E/MAX13204E/MAX13206E/MAX13208E
low-capacitance ±30kV ESD-protection diode arrays
are designed to protect sensitive electronics attached
to communication lines. Each channel consists of a pair
of diodes that steer ESD current pulses to V
CC
or GND.
The MAX13202E/MAX13204E/MAX13206E/MAX13208E
protect against ESD pulses up to ±15kV Human Body
Model (HBM) and ±30kV Air-Gap Discharge, as speci-
fied in IEC 61000-4-2. These devices have a 6pF on-
capacitance per channel, making them ideal for use on
high-speed data I/O interfaces.
The MAX13204E is a quad-ESD structure designed for
Ethernet and FireWire
®
applications. The MAX13202E/
MAX13206E/MAX13208E are 2-channel, 6-channel,
and 8-channel devices. They are designed for cell-
phone connectors and SVGA video connections.
These devices are available in 6-, 8-, and 10-pin µDFN
packages and are specified over the -40°C to +125°C
automotive operating temperature range.
Features
♦
High-Speed Data-Line ESD Protection
±15kV—Human Body Model
±30kV—IEC 61000-4-2, Air-Gap Discharge
♦
Tiny µDFN Package
MAX13202E (1mm x 1.5mm)
MAX13204E (2mm x 2mm)
MAX13206E (2mm x 2mm)
MAX13208E (2mm x 2mm)
♦
Low 6pF Input Capacitance
♦
Low 1nA (max) Leakage Current
♦
+0.9V to +16V Supply Voltage Range
MAX13202E/MAX13204E/MAX13206E/MAX13208E
Ordering Information
PART
MAX13202EALT+
MAX13204EALT+
MAX13206EALA+
MAX13208EALB+
PIN-
PKG
6
µDFN
6
µDFN
8
µDFN
10
µDFN
PROTECTED
I/O PORTS
2
4
6
8
TOP
MARK
BV
AAO
AAL
AAD
PKG
CODE
L611-1
L622-1
L822-1
L1022-1
Applications
USB
USB 2.0
PDAs
FireWire
Ethernet
Video
Cell Phones
Pin Configurations
GND
N.C.
I/O2
Note:
All devices are specified over the -40°C to +125°C auto-
motive operating temperature range.
+Denotes
lead-free package
Typical Operating Circuit
V
CC
V
CC
6
5
4
MAX13202E
+
1
V
CC
2
N.C.
3
I/O1
0.1µF
PROTECTED
CIRCUIT
I/0
I/0_
0.1µF
µDFN
(1mm x 1.5mm)
Pin Configurations continued at end of data sheet.
MAX13202E
MAX13204E
MAX13206E
MAX13208E
FireWire is a registered trademark of Apple Computer, Inc.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
2-/4-/6-/8-Channel, ±30kV ESD Protectors in µDFN
MAX13202E/MAX13204E/MAX13206E/MAX13208E
ABSOLUTE MAXIMUM RATINGS
V
CC
to GND ............................................................-0.3V to +18V
I/O_ to GND ................................................-0.3V to (V
CC
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
6-Pin, 1mm x 1.5mm µDFN (derate 2.1mW/°C
above +70°C)................................................................168mW
6-Pin, 2mm x 2mm µDFN (derate 4.5mW/°C
above +70°C)................................................................358mW
8-Pin, 2mm x 2mm µDFN (derate 4.8mW/°C
above +70°C)................................................................381mW
10-Pin, 2mm x 2mm µDFN (derate 5.0mW/°C
above +70°C)................................................................403mW
Operating Temperature Range .........................-40°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature .....................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +5V ±5%, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at V
CC
= +5V and T
A
= +25°C.) (Note 1)
PARAMETER
Supply Voltage
Supply Current
Diode Forward Voltage
SYMBOL
V
CC
I
CC
V
F
I
F
= 10mA
T
A
= +25°C, ±15kV,
Human Body Model,
I
F
= 10A
Channel Clamp Voltage
(Note 2)
V
C
T
A
= +25°C, ±14kV,
Contact Discharge
(IEC 61000-4-2), I
F
= 42A
T
A
= +25°C, ±30kV,
Air-Gap Discharge
(IEC 61000-4-2), I
F
= 90A
Channel Leakage Current
(Note 3)
Channel Input Capacitance
ESD PROTECTION
Human Body Model
IEC 61000-4-2
Contact Discharge
IEC 61000-4-2
Air-Gap Discharge
MAX13204E/MAX13206E/MAX13208E
MAX13202E
±15
±14
±12
±30
kV
kV
kV
T
A
= -40°C to +50°C
T
A
= -40°C to +125°C
V
CC
= 5V, bias of V
CC
/2, f = 1MHz (Note 3)
Positive transients
Negative transients
Positive transients
Negative transients
Positive transients
Negative transients
-1
-1
6
0.65
CONDITIONS
MIN
0.9
1
TYP
MAX
16.0
100
0.95
V
CC
+ 25
-25
V
CC
+ 80
V
-80
V
CC
+ 120
-120
+1
+1
7
nA
µA
pF
UNITS
V
nA
V
Note 1:
Limits over temperature are guaranteed by design, not production tested.
Note 2:
Idealized clamp voltages (L1 = L2 = L3 = 0) (Figure 1); see the
Applications Information
section for more information.
Note 3:
Guaranteed by design. Not production tested.
2
_______________________________________________________________________________________
2-/4-/6-/8-Channel, ±30kV ESD Protectors in µDFN
MAX13202E/MAX13204E/MAX13206E/MAX13208E
Typical Operating Characteristics
(V
CC
= +5V, T
A
= +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. TEMPERATURE
MAX13204E//6E/8E toc01
CLAMP VOLTAGE
vs. DC CURRENT
MAX13204E//6E/8E toc02
I/O LEAKAGE CURRENT
vs. TEMPERATURE
MAX13204E//6E/8E toc03
100
1.1
10
10
SUPPLY CURRENT (nA)
I/O LEAKAGE CURRENT (nA)
CLAMP VOLTAGE (V)
1.0
I/O TO V
CC
0.9
1
V
CC
= 12V
V
CC
= 5V
0.1
1
V
CC
= 12V
0.1
0.8
0.01
V
CC
= 5V
0.001
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
V
CC
= 3.3V
0.7
30
50
70
90
I/O TO GND
0.01
V
CC
= 3.3V
0.001
110
130
150
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
DC CURRENT (mA)
INPUT CAPACITANCE
vs. INPUT VOLTAGE
MAX13204E/6E/8E toc04
INPUT CAPACITANCE
vs. INPUT VOLTAGE
9
INPUT CAPACITANCE (pF)
8
7
6
5
4
3
2
1
0
V
CC
= 12V
MAX13204E/6E/8E toc05
14
13
12
INPUT CAPCITANCE (pF)
11
10
9
8
7
6
5
4
0
1
2
3
4
5
INPUT VOLTAGE (V)
V
CC
= 5.0V
V
CC
= 3.3V
10
0
1
2
3
4
5
6
7
8
9 10 11 12
INPUT VOLTAGE (V)
Pin Description
PIN
MAX13202E
1
2, 5
3, 4
6
MAX13204E
1
—
2–5
6
MAX13206E
1
—
2–7
8
MAX13208E
1
—
2–9
10
NAME
FUNCTION
V
CC
N.C.
I/O_
GND
Power-Supply Input. Bypass V
CC
to GND with a 0.1µF ceramic capacitor.
Place the capacitor as close as possible to the device.
No Connection. Not internally connected.
ESD-Protected Channel
Ground
_______________________________________________________________________________________
3
2-/4-/6-/8-Channel, ±30kV ESD Protectors in µDFN
MAX13202E/MAX13204E/MAX13206E/MAX13208E
Detailed Description
The MAX13202E/MAX13204E/MAX13206E/MAX13208E
are diode arrays designed to protect sensitive electron-
ics against damage resulting from ESD conditions or
transient voltages. The low input capacitance makes
these devices ideal for high-speed data lines. The
MAX13202E/MAX13204E/MAX13206E/MAX13208E
protect two, four, six, and eight channels, respectively.
The MAX13202E/MAX13204E/MAX13206E/MAX13208E
are designed to work in conjunction with a device’s
intrinsic ESD protection. The MAX13202E/MAX13204E/
MAX13206E/MAX13208E limit the excursion of the ESD
event to below ±25V peak voltage when subjected to the
Human Body Model waveform. When subjected to the
IEC 61000-4-2 waveform, the peak voltage is limited to
±80V (Contact Discharge) and ±120V (Air-Gap
Discharge). The device that is being protected by the
MAX13202E/MAX13204E/ MAX13206E/MAX13208E
must be able to withstand these peak voltages plus any
additional voltage generated by the parasitic board.
d(I
ESD
)
d(I
ESD
)
V
C
= −
V
F
(
D2
)
+
L1 x
+
L3 x
dt
dt
where I
ESD
is the ESD current pulse.
POSITIVE SUPPLY RAIL
L2
D1
L1
I/O_
PROTECTED
LINE
D2
L3
GROUND RAIL
Applications Information
Design Considerations
Maximum protection against ESD damage results from
proper board layout (see the
Layout Recommendations
section and Figure 2). A good layout reduces the para-
sitic series inductance on the ground line, supply line,
and protected signal lines.
The MAX13202E/MAX13204E/MAX13206E/MAX13208E
ESD diodes clamp the voltage on the protected lines
during an ESD event and shunt the current to GND or
V
CC
. In an ideal circuit, the clamping voltage, V
C
, is
defined as the forward voltage drop, V
F
, of the protection
diode plus any supply voltage present on the cathode.
For positive ESD pulses:
V
C
= V
CC
+ V
F
For negative ESD pulses:
V
C
= -V
F
In reality, the effect of the parasitic series inductance
on the lines must also be considered (Figure 1).
For positive ESD pulses:
d(I
ESD
)
d(I
ESD
)
V
C
=
V
CC
+
V
F
(
D1
)
+
L1 x
+
L2 x
dt
dt
Figure 2. Layout Considerations
Figure 1. Parasitic Series Inductance
V
CC
L1
PROTECTED LINE
NEGATIVE ESD
CURRENT
PULSE
PATH TO
GROUND
L2
D1
V
C
I/O_
D2
L3
PROTECTED
CIRCUIT
GND
For negative ESD pulses:
4
_______________________________________________________________________________________
2-/4-/6-/8-Channel, ±30kV ESD Protectors in µDFN
During an ESD event, the current pulse rises from zero
to peak value in nanoseconds (Figure 3). For example,
in a ±15kV IEC-61000-4-2 Air-Gap Discharge ESD
event, the pulse current rises to approximately 45A in
1ns (di/dt = 45 x 10
9
). An inductance of only 10nH adds
an additional 450V to the clamp voltage. An inductance
of 10nH represents approximately 0.5in of board trace.
Regardless of the device’s specified diode clamp volt-
age, a poor layout with parasitic inductance significantly
increases the effective clamp voltage at the protected
signal line.
A low-ESR 0.1µF capacitor must be used between V
CC
and GND. This bypass capacitor absorbs the charge
transferred by a +14kV (MAX13204E/MAX13206E/
MAX13208E) and ±12kV (MAX13202E) IEC61000-4-2
Contact Discharge ESD event.
Ideally, the supply rail (V
CC
) would absorb the charge
caused by a positive ESD strike without changing its
regulated value. In reality, all power supplies have an
effective output impedance on their positive rails. If a
power supply’s effective output impedance is 1Ω, then
by using V = I
×
R, the clamping voltage of V
C
increas-
es by the equation V
C
= I
ESD
x R
OUT
. An ±8kV
IEC 61000-4-2 ESD event generates a current spike of
24A, so the clamping voltage increases by V
C
= 24A
×
1Ω, or V
C
= 24V. Again, a poor layout without proper
bypassing increases the clamping voltage. A ceramic
chip capacitor mounted as close to the MAX13202E/
MAX13204E/MAX13206E/MAX13208E V
CC
pin is the
best choice for this application. A bypass capacitor
should also be placed as close to the protected device
as possible.
±30kV ESD Protection
ESD protection can be tested in various ways. The
MAX13202E/MAX13204E/MAX13206E/MAX13208E are
characterized for protection to the following limits:
• ±15kV using the Human Body Model
• ±14kV (MAX13204E/MAX13206E/MAX13208E) and
±12kV (MAX13202E) using the Contact Discharge
method specified in IEC 61000-4-2
• ±30kV using the IEC 61000-4-2 Air-Gap Discharge
method
ESD Test Conditions
ESD performance depends on a number of conditions.
Contact Maxim for a reliability report that documents
test setup, methodology, and results.
MAX13202E/MAX13204E/MAX13206E/MAX13208E
R
C
1MΩ
CHARGE-CURRENT-
LIMIT RESISTOR
HIGH-
VOLTAGE
DC
SOURCE
R
D
1.5kΩ
DISCHARGE
RESISTANCE
DEVICE
UNDER
TEST
Cs
100pF
STORAGE
CAPACITOR
Figure 4. Human Body ESD Test Model
I
100%
90%
I
PEAK
I
P
100%
90%
AMPERES
36.8%
Ir
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
10%
t
R
= 0.7ns to 1ns
30ns
60ns
t
10%
0
0
t
RL
TIME
t
DL
CURRENT WAVEFORM
Figure 3. IEC 61000-4-2 ESD Generator Current Waveform
Figure 5. Human Body Model Current Waveform
5
_______________________________________________________________________________________
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