19-0703; Rev 1; 5/08
MAX19692/MAX19693 Evaluation Kits
General Description
The MAX19692/MAX19693 evaluation kits (EV kits) are
fully assembled and tested PCBs that contain all the
components necessary to evaluate the performance of
the MAX19692 2.3Gsps and MAX19693 4.0Gsps 12-bit,
direct RF synthesis digital-to-analog converters (DACs).
The EV kit boards include wideband transformers for
differential-to-single-ended conversion of the DAC out-
put and for single-ended-to-differential conversion of
the DAC clock.
Features
o
2.3Gsps Maximum DAC Update Rate (MAX19692)
o
4.0Gsps Maximum DAC Update Rate (MAX19693)
o
Direct Interface with Maxim HSDCEP Data Source
Board Using QSH Connectors
o
Proven 12-Layer PCB Design
o
On-Board Reference Circuitry
o
On-Board Power-On Reset
o
On-Board Clock Interface
2.3GHz Maximum Clock Rate (MAX19692)
2.0GHz Maximum Clock Rate (MAX19693)
o
Wideband Output Transformer
Supports from < 30MHz to > 2000MHz
o
Fully Assembled and Tested
o
Data Source (FPGA) Board Available
(Order HSDCEP)
Evaluate: MAX19692/MAX19693
Ordering Information
PART
MAX19692EVKIT
MAX19693EVKIT
LVDSADPB12+
TYPE
EV Kit
EV Kit
Adapter Board
+Denotes
lead-free and RoHS compliant.
Component Lists
MAX19692/MAX19693 EV Kits
DESIGNATION
CLK, OUT
QTY
2
DESCRIPTION
0.92in SMA connectors (PC edge
mount)
100pF ±5%, 50V C0G ceramic
capacitors (0402)
TDK C1005C0G1H101J or
Murata GRM1555C1H101J
0.1µF ±20%, 10V X5R ceramic
capacitors (0402)
TDK C1005X5R1A104M
1µF ±20%, 6.3V X5R ceramic
capacitors (0402)
TDK C1005X5R0J105M
Not installed, ceramic capacitors
(0603)
47µF ±20% 16V tantalum capacitors
(C case)
AVX TPSC476M016R0350 or
Vishay 594D476X0016C2T
10µF ±20%, 6.3V X5R ceramic
capacitors (0805)
TDK C2012X5R0J106M or
Murata GRM21BR60J106M
0.1µF ±20% 6.3V X5R ceramic
capacitors (0201)
TDK C0603X5R0J104M
Not installed, SMA PC-mount
connectors (vertical)
DESIGNATION
H1, H2
JU1, JU2, JU7,
JU8
JU3, JU4, JU5,
JU9*
JU6
L1, L2, L3
QTY
2
DESCRIPTION
Vertical 2 x 60 surface-mount high-
speed socket connectors
Samtec QSH-060-01-L-D-A
2-pin headers
3-pin headers
Not installed, 2-pin header
Chip bead cores (1812)
Panasonic EXC-CL4532U1
2.2µH wire-wound chip inductors
(2520)
Coilcraft 1008CS-222XJLB
10kΩ ±5% resistors (0402)
Not installed, resistors (0402)
Not installed, resistor (0603)
49.9Ω ±1% resistors (0402)
2.0kΩ ±0.1% resistor (0402)
499Ω ±1% resistor (0402)
174kΩ ±1% resistors (0603)
100kΩ ±1% resistors (0603)
Momentary pushbutton switch
1:1 3000MHz RF transformers
Mini-Circuits TC1-1-13M+
Not Installed, PC test point
C1, C2
2
4
4
0
3
C3, C4, C12,
C13
C5–C8,
C24–C31
C9, C10, C11
4
12
L4, L5
R1
R2, R3
R4
R5, R6
R7
R8
R9, R11
R10, R12
SW1
T1–T4
TP1
2
1
0
0
2
1
1
2
2
1
4
0
0
C14, C15, C16
3
C17–C23
7
C32–C47
DATA-CLKN,
DATA-CLKP
16
0
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX19692/MAX19693 Evaluation Kits
Evaluate: MAX19692/MAX19693
Component Lists (continued)
DESIGNATION
U1
QTY
1
DESCRIPTION
See the
EV Kit-Specific Component
List
High-accuracy supervisory circuit
(6 SOT23)
Maxim MAX6710LUT+
(Top Mark: AAZL)
1.25V precision voltage reference
(8 SO)
Maxim MAX6161AESA+ or
Maxim MAX6161BESA+
Shunts (JU1–JU5, JU7, JU8, JU9*)
PCB: MAX19692/MAX19693
Evaluation Kit
LVDSADPB12 Adapter Board
DESIGNATION
H1A, H2A
J1–J4
—
QTY
2
4
1
DESCRIPTION
Vertical 2 x 60 surface-mount high-
speed socket connectors
Samtec QTH-060-01-F-D-A
Dual-row, 48-pin (2 x 24) headers
PCB: 12-Bit LVDS Adapter Board+
U2
1
Component Suppliers
SUPPLIER
AVX Corporation
Coilcraft, Inc.
PHONE
WEBSITE
843-946-0238 www.avxcorp.com
847-639-6400 www.coilcraft.com
U3
1
—
—
8
1
Murata Electronics
770-436-1300 www.murata-northamerica.com
North America, Inc.
Panasonic Corp.
TDK Corp.
Vishay
800-344-2112 www.panasonic.com
847-803-6100 www.component.tdk.com
402-563-6866 www.vishay.com
*Not
installed on the MAX19693 EV kit.
EV Kit-Specific Component List
EV KIT PART
NUMBER
MAX19692EVKIT
U1
MAX19693EVKIT
DESIGNATION
DESCRIPTION
12-bit, 2.3Gsps, D-to-A
converter (169 CSBGA)
Maxim MAX19692EXW-D
12-bit, 4.0Gsps, D-to-A
converter (169 CSBGA)
Maxim MAX19693EXW-D
Note:
Indicate that you are using the MAX19692 or MAX19693
when contacting these component suppliers.
Quick Start
Required Equipment
Before beginning, the following equipment is needed:
• Two 1.8V, 1A DC power supplies
•
•
•
•
•
One 3.3V, 1A DC power supply
Signal generator with low phase noise and low jitter
for clock input signal (e.g., Agilent 8665B)
One high-performance spectrum analyzer (e.g.,
Rohde & Schwarz FSU or Agilent PSA)
One Maxim HSDCEP data source board
(Optional) One Maxim LVDS adapter board when
using a pattern generator with 0.1in header con-
nectors (order the LVDSADPB12+ adapter board
from Maxim Integrated Products, Inc.)
Procedure
The EV kits are fully assembled and tested. Follow the
steps below to verify board operation.
Caution: Do not
turn on the power supplies or signal sources until
all connections are completed.
2
1) Verify that shunts are installed in the following posi-
tions:
JU1, JU2 (installed)
→
On-board reference
enabled
JU3 (2-3)
→
No delay added
JU4 (2-3)
→
Modulation disabled (MAX19693
EV kit)
JU4, JU9 (2-3)
→
Normal DAC (NRZ) operation
(MAX19692 EV kit)
JU5 (1-2)
→
DDR mode
JU7 (installed)
→
Scan disabled (MAX19693 EV
kit)/connect pin to ground (GND) (MAX19692 EV
kit)
JU8 (installed)
→
Calibration circuit enabled
2) Connect a 1.8V DC power supply to the VDD1.8
and GND pads.
3) Connect a 1.8V DC power supply to the AVCLK and
GND pads.
4) Connect a 3.3V DC power supply to the AVDD3.3
and GND pads.
5) Connect the clock signal generator to the EV kit
SMA connector labeled CLK.
6) Connect the Maxim HSDCEP data source board to
connectors H1 and H2 on the EV kit. Download
the latest version of the MAX19692 or MAX19693
EV kit firmware to the HSDCEP data source board
_______________________________________________________________________________________
MAX19692/MAX19693 Evaluation Kits
from www.maxim-ic.com/HSDCEP_Firmware and
refer to the HSDCEP data sheet for upload and
installation instructions. See the
Using the HSDCEP
Data Source Board with the EV Kit
section.
7) Connect the spectrum analyzer to the EV kit SMA
connector labeled OUT.
8) Turn on all the DC power supplies.
9) Enable the HSDCEP data source board.
10) Observe the output spectrum on the spectrum
analyzer.
The EV kit circuit features three reference options. Use
the DAC’s internal voltage reference by removing the
shunts from jumpers JU1 and JU2. Use an external ref-
erence by removing the shunts from jumpers JU1 and
JU2 and connecting a stable voltage reference at the
REFIO pad. Install shunts on jumpers JU1 and JU2 to
use the EV kit’s on-board reference (MAX6161). See
Table 1 to configure the shunts across jumpers JU1
and JU2 and select the source of the reference voltage.
Evaluate: MAX19692/MAX19693
Detailed Description of Hardware
The MAX19692 and MAX19693 EV kits are designed to
simplify the evaluation of the MAX19692 2.3Gsps and
MAX19693 4.0Gsps 12-bit, direct RF synthesis DACs.
Each EV kit operates with LVDS data inputs, a single-
ended clock input signal, and 1.8V/3.3V power supplies
for simple board operation.
The EV kit PCB features on-board QSH connectors that
interface directly to the Maxim HSDCEP data source
board, circuitry that converts the differential 50Ω output
to a single-ended 50Ω signal, and circuitry to convert a
user-supplied single-ended clock signal to a differential
clock required by the DAC. The EV kit also includes
jumpers that configure frequency response, modula-
tion, scan, reference voltage, calibration, and data
clock modes.
Table 1. Reference Voltage Selection
(JU1, JU2)
SHUNT
POSITIONS
Installed*
VOLTAGE REFERENCE MODE
External 1.25V reference (U3) connected to
DAC’s REFIO pin
DAC’s internal 1.2V bandgap reference
Not Installed
User-supplied voltage reference at the REFIO
pad (0.5V to 1.8V)
*Default
position: JU1 (installed), JU2 (installed).
The full-scale output power is dependent on the value
of the reference voltage and the value of resistor R7.
Use the equation below to calculate the DAC full-scale
output power:
⎡⎛
⎞⎤
V
REFIO
×
23.5
⎟ ⎥
⎢ ⎜
32
×
R7
⎝
⎠⎥
P
OUT
=
20
×
log
⎢
dBm
]
⎢
⎥
[
0.6328
⎢
⎥
⎣
⎦
where:
P
OUT
= DAC full-scale output power
V
REFIO
= voltage present at the REFIO pad (V
REFIO
=
1.2V when using the DAC’s internal reference)
R7 = value of resistor R7 in ohms (2kΩ default)
Power Supplies
Each EV kit operates from two 1.8V and one 3.3V power
supplies. The two separate 1.8V power supplies can be
driven from the same source. Each power plane on the
EV kit PCB is filtered for optimum dynamic performance.
Clock Signal
Each DAC requires a differential clock input signal
with minimal jitter. The EV kits feature single-ended-
to-differential-conversion circuitry. Supply a single-
ended clock signal at the SMA connector labeled CLK.
The power applied to the SMA should be between
+10dBm and +15dBm when measured at the con-
nector. Insertion losses due to the interconnecting
cable decrease the power seen at the EV kit input.
Account for these losses when setting the signal gen-
erator amplitude.
Data Clock Division
The data clock output differential signal (DATACLK)
frequency is scaled down from the DAC clock input.
Jumper JU5 controls the division factor. See Table 2
for shunt settings. Refer to the IC data sheet for
details on synchronizing the DAC to an external pat-
tern generator. Install resistors R2, R3, and R4 to
access the differential output data clock signal at the
DATA-CLKP and DATA-CLKN SMA connectors on the
EV kit board when not using the Maxim HSDCEP data
source board.
3
Reference Voltage Options
The DAC requires a reference voltage to set its output
power. The DAC features a stable on-chip bandgap ref-
erence of 1.2V. The internal reference can be overdriv-
en by an external reference to enhance accuracy and
drift performance or for gain control.
_______________________________________________________________________________________
MAX19692/MAX19693 Evaluation Kits
Evaluate: MAX19692/MAX19693
Table 2. Data Clock Division (JU5)
SHUNT
POSITION
1-2
2-3*
CLKDIV PIN
Connected to
AVDD3.3
Connected to
GND
EV KIT FUNCTION
DDR mode:
DATACLK = input data rate/2
QDR mode:
DATACLK = input data rate/4
Modulation (MAX19693)
The MAX19693 f
DAC
/2 (or f
CLK
) modulation mode can
be enabled or disabled by connecting the MOD pin to
3.3V or to ground. The EV kit circuit provides jumper
JU4 to configure the MOD pin. Refer to the MAX19693
IC data sheet for more details on the MOD pin. See
Table 5 for jumper JU4 configuration.
Table 5. Modulation Configuration (JU4)
SHUNT
POSITION
1-2
2-3*
MOD PIN
Connected to AVDD3.3
Connected to GND
MODULATION MODE
Enabled
Disabled
*Default
position.
Data Clock Delay
Jumper JU3 adjusts the delay of the data clock output.
Refer to the
Data Timing Relationships
section in the IC
data sheet for more details. See Table 3 for shunt settings.
Table 3. Data Clock Delay (JU3)
SHUNT
POSITION
1-2
2-3*
DELAY PIN
Connected to
AVDD3.3
Connected to
GND
EV KIT FUNCTION
Delay of 1/2 input data period
No delay added
*Default
position.
Output Resistor Calibration
The EV kit circuit features an on-board µP supervisor
(U2) to generate the CAL signal required to calibrate
the integrated output termination resistors. At power-up,
the supervisor applies a logic-high to the CAL pin
140ms after the final supply voltage is within its speci-
fied range. Pressing switch SW1 recalibrates the inte-
grated termination resistors by creating a logic-low
pulse on the CAL pin. The shunt on jumper JU8 can be
removed to apply an external logic signal to pin 1 of
jumper JU8 and initiate a CAL operation. See Table 6
for jumper JU8 configuration. Refer to the IC data sheet
for details on the CAL operation.
*Default
position.
Differential Output
The DAC features a differential output with built-in self-
calibrated output termination resistors. The EV kit pulls
the outputs up to AVDD3.3 through on-board bias
inductors L4 and L5 to optimize performance of the
device. Balun transformer T1 converts the differential
signal to a single-ended signal. Measure the resulting
DAC output at the SMA connector labeled OUT.
Table 6. Calibration Configuration (JU8)
SHUNT
POSITION
Installed*
Not
installed
CAL PIN
Connected to U2
RESET
pin
Not connected
EV KIT FUNCTION
Calibration initiated by
µP supervisor U2
User-supplied logic
signal at pin 1 of
jumper JU8
Impulse/Frequency Response (MAX19692)
The MAX19692 DAC has three impulse/frequency
response modes: NRZ, RZ, and RF. These modes are set
with the RZ and RF input pins. The MAX19692 EV kit pro-
vides jumpers JU4 and JU9 to configure these pins. See
Table 4 for jumpers JU4 and JU9 configuration. Refer
to the
DAC Impulse/Frequency Response Modes
section
in the MAX19692 IC data sheet for more details.
*Default
position.
Input Register Scan (MAX19693)
The MAX19693 scan function can be enabled or dis-
abled by configuring the SE pin. When the scan func-
tion is enabled, the contents of the input register are
shifted out on the SO pin. Connect a digital sampling
device to pin 1 of JU6 to access the scan output data
on the SO pin. The EV kit circuit provides jumper JU7,
which is used to enable or disable the scan function.
During normal operation, install the shunt across
jumper JU7 to disable the scan function. Refer to the
MAX19693 IC data sheet for more details. See Table 7
for jumper JU7 configuration.
Table 4. RZ and RF Input Configuration
(JU4, JU9)
SHUNT POSITION
JU4
2-3*
2-3
1-2
JU9
2-3*
1-2
2-3
FREQUENCY
RESPONSE MODE
NRZ
RZ
RF
*Default
position.
4
_______________________________________________________________________________________
MAX19692/MAX19693 Evaluation Kits
Table 7. Scan Configuration (JU7)
SHUNT
POSITION
Installed*
Not
installed
SE PIN
Connected to GND
Not connected (SE pin
internally pulled down
to ground GND)
SCAN FUNCTION
Scan disabled
User must supply a
1.8V CMOS logic signal
to pin 1 of jumper JU7
to enable scan
Refer to the HSDCEP data sheet for specifics on sys-
tem requirements, software installation, loading config-
uration file, and data pattern file format.
Evaluate: MAX19692/MAX19693
Table 9. EV Kit Configuration for Use with
the HSDCEP
JUMPER
JU3
JU5
SHUNT
POSITION
2-3
1-2
EV KIT FUNCTION
No delay added to DATACLK
EV kit interface in DDR mode
*Default
position.
Using the HSDCEP Data Source
Board with the EV Kit
The high-speed data converter evaluation platform
(HSDCEP) can be used as a high-speed data source
for the EV kit. Test patterns can be generated using a
PC and uploaded to the HSDCEP for evaluation of the
MAX19692 or MAX19693 EV kits. EV kit-specific
firmware load is required to configure the HSDCEP. The
most up-to-date firmware can be downloaded from
www.maxim-ic.com/HSDCEP_Firmware. When loading
the HSDCEP firmware for the DAC, select the appropri-
ate firmware version based on the DAC’s update rate
(see Table 8). See Table 9 for EV kit jumper configura-
tion when using the HSDCEP.
Connecting the HSDCEP to the EV Kit
The HSDCEP and EV kit boards can be connected
using the hardware supplied with the EV kit. See Figure
1 for details when connecting the boards together.
Alternatively, the two boards can be connected with
coaxial ribbon cables (Samtec, Part No. HQCD-060.00-
STR-TBR-1). Note that it is necessary to use either the
supplied hardware or cables to obtain a reliable electri-
cal connection between the two boards.
Interfacing the EV Kit
to a Pattern Generator
The EV kit provides QSH connectors (H1 and H2) to
connect to Maxim’s HSDCEP data source board. If the
HSDCEP is not available, order the 12-bit LVDS adapter
board (LVDSADPB12+) and connect it to connectors
H1 and H2. Interface a 48-bit LVDS pattern generator to
the 0.1in 2 x 24 headers (J1–J4) on the adapter board.
The header data pins are labeled on the board with
their appropriate data bit designation. Table 10 details
header connections for J1 through J4. Use the labels
on the LVDS adapter board or Table 10 to match the
data bits from the pattern generator to the correspond-
ing data pins on headers J1 through J4.
Table 8. Firmware Select
DAC UPDATE RATE
≥
1Gsps
< 1Gsps
FIRMWARE VERSION
MAX19692_DDR_revYY.bit or
MAX19693_DDR_revYY.bit
MAX19692slow_DDR_revYY.bit or
MAX19693slow_DDR_revYY.bit
_______________________________________________________________________________________
5
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