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FIR-COMP-E5-UT: 产品描述开发软件 FIR FILTER FOR ECP5 - SITE LICENSE; 产品类别嵌入式解决方案工程工具开发软件; 文件大小2MB，共41页; 制造商Lattice(莱迪斯); 官网地址http://www.latticesemi.com; 标准

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FIR-COMP-E5-UT概述

开发软件 FIR FILTER FOR ECP5 - SITE LICENSE

FIR-COMP-E5-UT规格参数

参数名称	属性值
厂商名称	Lattice(莱迪斯)
产品种类	开发软件
发货限制	Mouser目前不销售该产品。
产品	IP Core
用于	Lattice ECP5
封装	Tray
工厂包装数量	1

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FIR Filter IP Core

User Guide

FPGA-IPUG-02043 Version 1.5

June 2018

FIR Filter IP Core

User Guide

Contents

Acronyms in This Document .................................................................................................................................................5

1. Introduction ..................................................................................................................................................................6

2. Quick Facts ....................................................................................................................................................................7

3. Features ........................................................................................................................................................................9

4. Functional Description ................................................................................................................................................10

4.1.

Interface Diagram..............................................................................................................................................10

4.2.

FIR Filter Architecture .......................................................................................................................................10

4.2.1. Direct-form Implementation.........................................................................................................................10

4.2.2. Symmetric Implementation ..........................................................................................................................11

4.2.3. Polyphase Interpolation FIR Filter .................................................................................................................11

4.2.4. Polyphase Decimation FIR Filter ...................................................................................................................12

4.2.5. Multi-channel FIR Filters ...............................................................................................................................12

4.3.

Implementation Details .....................................................................................................................................12

4.4.

Configuring the FIR Filter Core ..........................................................................................................................14

4.4.1. Architecture Options.....................................................................................................................................14

4.4.1.1.

Coefficients Specification .....................................................................................................................14

4.4.1.2.

Multiplier Multiplexing Factor .............................................................................................................15

4.4.2. I/O Specification Options ..............................................................................................................................15

4.4.2.1.

Rounding ..............................................................................................................................................15

4.4.3. Implementation Options ...............................................................................................................................15

4.4.3.1.

Memory Type .......................................................................................................................................15

4.5.

Signal Descriptions ............................................................................................................................................16

4.6.

Interfacing with the FIR Filter IP Core ...............................................................................................................17

4.6.1. Data interface ...............................................................................................................................................17

4.6.2. Multiple Channels .........................................................................................................................................17

4.6.3. Variable Interpolation/Decimation Factor ....................................................................................................17

4.6.4. Reloadable Coefficients ................................................................................................................................17

4.7.

Timing Specifications .........................................................................................................................................18

4.7.1. Timing Specifications Applicable to All Devices ............................................................................................18

4.7.2. Timing Specifications Applicable to LatticeXP2, LatticeECP3 and LatticeECP5 Implementations ................19

4.7.3. Timing Specifications Applicable to LatticeECP3 and LatticeECP5 Implementations ...................................20

5. Parameter Settings .....................................................................................................................................................21

5.1.

Architecture Tab ................................................................................................................................................22

5.2.

I/O Specification Tab .........................................................................................................................................24

5.3.

Implementation Tab ..........................................................................................................................................26

6. IP Core Generation and Evaluation.............................................................................................................................27

6.1.

Licensing the IP Core .........................................................................................................................................27

6.2.

Getting Started ..................................................................................................................................................27

6.3.

IPexpress-Created Files and Top Level Directory Structure ..............................................................................31

6.4.

Instantiating the Core........................................................................................................................................32

6.5.

Running Functional Simulation .........................................................................................................................32

6.6.

Synthesizing and Implementing the Core in a Top-Level Design.......................................................................32

6.7.

Hardware Evaluation .........................................................................................................................................33

6.7.1. Enabling Hardware Evaluation in Diamond...................................................................................................33

6.8.

Updating/Regenerating the IP Core ...................................................................................................................33

6.8.1. Regenerating an IP Core in Diamond ............................................................................................................33

6.9.

Regenerating an IP Core in Clarity Designer Tool ..............................................................................................34

6.10. Recreating an IP Core in Clarity Designer Tool ..................................................................................................34

References ..........................................................................................................................................................................35

Technical Support Assistance .............................................................................................................................................36

Appendix A. Resource Utilization .......................................................................................................................................37

LatticeECP3 Devices ........................................................................................................................................................37

www.latticesemi.com/legal.

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-IPUG-02043-1.5

FIR Filter IP Core

User Guide

Figures

Figure 4.1. Top-Level Interface for the FIR Filter IP Core ....................................................................................................10

Figure 4.2. Direct-form FIR Filter ........................................................................................................................................11

Figure 4.3. Symmetric Coefficients FIR Filter Implementation ...........................................................................................11

Figure 4.4. Polyphase Interpolator .....................................................................................................................................11

Figure 4.5. Polyphase Decimator ........................................................................................................................................12

Figure 4.6. Functional Block Diagram .................................................................................................................................13

Figure 4.7. Tap and Coefficient Memory Management for a Sample FIR Filter .................................................................13

Figure 4.8. Single Channel, Single Rate FIR Filter with Continuous Inputs .........................................................................18

Figure 4.9. Single Channel, Single Rate FIR Filter with Gaps in Input .................................................................................18

Figure 4.10. Factorset Signals .............................................................................................................................................18

Figure 4.11. Coefficient Reloading ......................................................................................................................................18

Figure 4.12. Multi-Channel Single Rate FIR Filter (3 Channels) ..........................................................................................19

Figure 4.13. Multi-Channel (3 Channels) Interpolator (Factor of 3) ...................................................................................19

Figure 4.14. Multi-Channel (3 Channels) Decimator (Factor of 3) ......................................................................................19

Figure 4.15. Multi-Channel Single Rate FIR Filter (3 Channels) ..........................................................................................20

Figure 4.16. Multi-Channel (3 Channels) Interpolator (Factor of 3) ...................................................................................20

Figure 4.17. Multi-Channel (3 Channels) Decimator (Factor of 3) ......................................................................................20

Figure 5.1. Architecture Tab of the FIR Filter IP Core Interface ..........................................................................................22

Figure 5.2. I/O Specification Tab of the FIR Filter IP Core Interface ...................................................................................24

Figure 5.3. Implementation Tab of the FIR Filter IP Core Interface ....................................................................................26

Figure 6.1. IPexpress Dialog Box .........................................................................................................................................27

Figure 6.2. Configuration Dialog Box ..................................................................................................................................28

Figure 6.3. Clarity Designer Tool Dialog Box .......................................................................................................................28

Figure 6.4. Clarity Designer Catalog Tab .............................................................................................................................29

Figure 6.5. Fir Filter Dialog Box ...........................................................................................................................................29

Figure 6.6. IP Configuration Interface .................................................................................................................................30

Figure 6.7. FIR Filter IP Core Generated Directory Structure..............................................................................................31

Tables

Table 2.1. FIR Filter IP Core for LatticeXP2 Devices Quick Facts ...........................................................................................7

Table 2.2. FIR Filter IP Core for LatticeECP3 Devices Quick Facts .........................................................................................7

Table 2.3. FIR Filter IP Core for LatticeECP5 Devices Quick Facts .........................................................................................8

Table 4.1. Maximum Multiplier Multiplexing Factor for Different Configurations* ...........................................................15

Table 4.2. Top-Level Port Definitions ..................................................................................................................................16

Table 5.1. Parameter Specifications for the FIR Filter IP Core ............................................................................................21

Table 5.2. Architecture Tab.................................................................................................................................................23

Table 5.3. I/O Specification Tab ..........................................................................................................................................25

Table 5.4. Implementation Tab ...........................................................................................................................................26

Table 6.1. File List ...............................................................................................................................................................31

Table A.1. Performance and Resource Utilization (LatticeECP3)* ......................................................................................37

Table A.2. Performance and Resource Utilization (LatticeXP2)* ........................................................................................37

Table A.3. Performance and Resource Utilization (LFE5U)* ...............................................................................................37

www.latticesemi.com/legal.

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-IPUG-02043-1.5

FIR-COMP-E5-UT相似产品对比

	FIR-COMP-E5-UT	FIR-COMP-E5-U
描述	开发软件 FIR FILTER FOR ECP5 - SITE LICENSE	开发软件 FIR FILTER FOR ECP5 - SINGLE DESIGN LICENSE
厂商名称	Lattice(莱迪斯)	Lattice(莱迪斯)
产品种类	开发软件	开发软件
发货限制	Mouser目前不销售该产品。	Mouser目前不销售该产品。
产品	IP Core	IP Core
用于	Lattice ECP5	Lattice ECP5
封装	Tray	Tray
工厂包装数量	1	1

FIR-COMP-E5-UT

FIR-COMP-E5-UT在线购买

FIR-COMP-E5-UT概述

FIR-COMP-E5-UT规格参数

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