MUN5234DW1,
NSBC124XDXV6
Dual NPN Bias Resistor
Transistors
R1 = 22 kW, R2 = 47 kW
NPN Transistors with Monolithic Bias
Resistor Network
This series of digital transistors is designed to replace a single
device and its external resistor bias network. The Bias Resistor
Transistor (BRT) contains a single transistor with a monolithic bias
network consisting of two resistors; a series base resistor and a
base-emitter resistor. The BRT eliminates these individual
components by integrating them into a single device. The use of a BRT
can reduce both system cost and board space.
Features
(3)
R
1
Q
1
Q
2
R
2
R
1
(5)
(6)
www.onsemi.com
PIN CONNECTIONS
(2)
(1)
R
2
•
•
•
•
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
S and NSV Prefix for Automotive and Other Applications
Requiring Unique Site and Control Change Requirements;
AEC-Q101 Qualified and PPAP Capable
•
These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS
(T
A
= 25°C, common for Q
1
and Q
2
, unless otherwise noted)
Rating
Collector-Base Voltage
Collector-Emitter Voltage
Collector Current − Continuous
Input Forward Voltage
Input Reverse Voltage
Symbol
V
CBO
V
CEO
I
C
V
IN(fwd)
V
IN(rev)
Max
50
50
100
40
7
Unit
Vdc
Vdc
mAdc
Vdc
Vdc
(4)
MARKING DIAGRAMS
6
SOT−363
CASE 419B
1
7L M
G
G
SOT−563
CASE 463A
1
7L M
G
G
7L
M
G
= Specific Device Code
= Date Code*
= Pb-Free Package
(Note: Microdot may be in either location)
*Date Code orientation may vary depending up-
on manufacturing location.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
Device
MUN5234DW1T1G
NSBC124XDXV6T1G
NSVBC124XDXV6T1G
Package
SOT−363
SOT−563
SOT−563
Shipping
†
3,000/Tape & Reel
4,000/Tape & Reel
4,000/Tape & Reel
†For information on tape and reel specifications, including part orientation and
tape sizes, please refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2012
1
July, 2018 − Rev. 1
Publication Order Number:
DTC124XD/D
MUN5234DW1, NSBC124XDXV6
THERMAL CHARACTERISTICS
Characteristic
MUN5234DW1 (SOT−363) ONE JUNCTION HEATED
Total Device Dissipation
T
A
= 25°C
(Note 1)
(Note 2)
Derate above 25°C
(Note 1)
(Note 2)
Thermal Resistance,
Junction to Ambient
(Note 1)
(Note 2)
P
D
187
256
1.5
2.0
R
qJA
670
490
mW
mW/°C
°C/W
Symbol
Max
Unit
MUN5234DW1 (SOT−363) BOTH JUNCTION HEATED
(Note 3)
Total Device Dissipation
(Note 1)
T
A
= 25°C
(Note 2)
Derate above 25°C
(Note 1)
(Note 2)
Thermal Resistance,
Junction to Ambient
(Note 2)
Thermal Resistance,
Junction to Lead (Note 1)
(Note 2)
Junction and Storage Temperature Range
NSBC124XDXV6 (SOT−563) ONE JUNCTION HEATED
Total Device Dissipation
(Note 1)
T
A
= 25°C
Derate above 25°C
(Note 1)
Thermal Resistance,
Junction to Ambient
(Note 1)
P
D
357
2.9
R
qJA
350
mW
mW/°C
°C/W
(Note 1)
P
D
250
385
2.0
3.0
R
qJA
493
325
°C/W
188
208
−55 to +150
°C
mW
mW/°C
°C/W
R
qJL
T
J
, T
stg
NSBC124XDXV6 (SOT−563) BOTH JUNCTION HEATED
(Note 3)
Total Device Dissipation
(Note 1)
T
A
= 25°C
Derate above 25°C
(Note 1)
Thermal Resistance,
Junction to Ambient
(Note 1)
P
D
500
4.0
R
qJA
T
J
, T
stg
250
−55 to +150
°C
mW
mW/°C
°C/W
Junction and Storage Temperature Range
1. FR−4 @ Minimum Pad.
2. FR−4 @ 1.0
×
1.0 Inch Pad.
3. Both junction heated values assume total power is sum of two equally powered channels.
www.onsemi.com
2
MUN5234DW1, NSBC124XDXV6
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C, common for Q
1
and Q
2
, unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Collector-Base Cutoff Current
(V
CB
= 50 V, I
E
= 0)
Collector-Emitter Cutoff Current
(V
CE
= 50 V, I
B
= 0)
Emitter-Base Cutoff Current
(V
EB
= 6.0 V, I
C
= 0)
Collector-Base Breakdown Voltage
(I
C
= 10
mA,
I
E
= 0)
Collector-Emitter Breakdown Voltage (Note 4)
(I
C
= 2.0 mA, I
B
= 0)
ON CHARACTERISTICS
DC Current Gain (Note 4)
(I
C
= 5.0 mA, V
CE
= 10 V)
Collector-Emitter Saturation Voltage (Note 4)
(I
C
= 10 mA, I
B
= 1.0 mA)
Input Voltage (Off)
(V
CE
= 5.0 V, I
C
= 100
mA)
Input Voltage (On)
(V
CE
= 0.2 V, I
C
= 3.0 mA)
Output Voltage (On)
(V
CC
= 5.0 V, V
B
= 2.5 V, R
L
= 1.0 kW)
Output Voltage (Off)
(V
CC
= 5.0 V, V
B
= 0.5 V, R
L
= 1.0 kW)
Input Resistor
Resistor Ratio
4. Pulsed Condition: Pulse Width = 300 ms, Duty Cycle
≤
2%.
h
FE
80
V
CE(sat)
−
V
i(off)
−
V
i(on)
−
V
OL
−
V
OH
4.9
R1
R
1
/R
2
15.4
0.38
−
22
0.47
−
28.6
0.56
kW
−
0.2
Vdc
1.3
−
Vdc
0.8
−
Vdc
−
0.25
Vdc
150
−
V
I
CBO
−
I
CEO
−
I
EBO
−
V
(BR)CBO
50
V
(BR)CEO
50
−
−
−
−
Vdc
−
0.13
Vdc
−
500
mAdc
−
100
nAdc
nAdc
Symbol
Min
Typ
Max
Unit
400
P
D
, POWER DISSIPATION (mW)
350
300
250
200
150
100
50
0
−50
−25
0
25
50
75
100
125
150
(1) (2)
(1) SOT−363; 1.0
×
1.0 Inch Pad
(2) SOT−563; Minimum Pad
AMBIENT TEMPERATURE (°C)
Figure 1. Derating Curve
www.onsemi.com
3
MUN5234DW1, NSBC124XDXV6
TYPICAL CHARACTERISTICS
MUN5234DW1, NSBC124XDXV6
V
CE(sat)
, COLLECTOR−EMITTER VOLTAGE (V)
1
I
C
/I
B
= 10
h
FE
, DC CURRENT GAIN
1000
V
CE
= 10 V
25°C
100
−55°C
150°C
25°C
0.1
150°C
10
−55°C
0.01
0
10
20
30
40
50
I
C
, COLLECTOR CURRENT (mA)
1
0.1
1
10
I
C
, COLLECTOR CURRENT (mA)
100
Figure 2. V
CE(sat)
vs. I
C
Figure 3. DC Current Gain
3.2
C
ob
, OUTPUT CAPACITANCE (pF)
I
C
, COLLECTOR CURRENT (mA)
2.8
2.4
2
1.6
1.2
0.8
0.4
0
0
10
20
30
40
50
f = 10 kHz
I
E
= 0 A
T
A
= 25°C
100
−55°C
10
1
25°C
0.1
150°C
V
O
= 5 V
0.01
0
4
8
12
16
20
24
28
V
R
, REVERSE VOLTAGE (V)
V
in
, INPUT VOLTAGE (V)
Figure 4. Output Capacitance
Figure 5. Output Current vs. Input Voltage
100
V
in
, INPUT VOLTAGE (V)
10
25°C
−55°C
1
150°C
0.1
0
V
O
= 0.2 V
10
20
30
40
I
C
, COLLECTOR CURRENT (mA)
50
Figure 6. Input Voltage vs. Output Current
www.onsemi.com
4
MUN5234DW1, NSBC124XDXV6
PACKAGE DIMENSIONS
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
2X
aaa H D
D
A
D
5
4
H
GAGE
PLANE
6
L2
E
1
2X
2
3
L
DETAIL A
E1
aaa C
bbb H D
2X 3 TIPS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-
SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDI-
TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOOT.
DIM
A
A1
A2
b
C
D
E
E1
e
L
L2
aaa
bbb
ccc
ddd
MILLIMETERS
MIN
NOM MAX
−−−
−−−
1.10
0.00
−−−
0.10
0.70
0.90
1.00
0.15
0.20
0.25
0.08
0.15
0.22
1.80
2.00
2.20
2.00
2.10
2.20
1.15
1.25
1.35
0.65 BSC
0.26
0.36
0.46
0.15 BSC
0.15
0.30
0.10
0.10
INCHES
NOM MAX
−−− 0.043
−−− 0.004
0.035 0.039
0.008 0.010
0.006 0.009
0.078 0.086
0.082 0.086
0.049 0.053
0.026 BSC
0.010 0.014 0.018
0.006 BSC
0.006
0.012
0.004
0.004
MIN
−−−
0.000
0.027
0.006
0.003
0.070
0.078
0.045
e
B
TOP VIEW
6X
b
ddd
M
C A-B D
A2
A
DETAIL A
6X
ccc C
SIDE VIEW
A1
C
SEATING
PLANE
c
END VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.30
6X
0.66
2.50
0.65
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
