MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM69D536/D
32K x 36 Bit Synchronous
Dual I/O, Dual Address SRAM
MCM69D536
Freescale Semiconductor, Inc...
The MCM69D536 is a 1M–bit static random access memory, organized as 32K
words of 36 bits. It features common data input and data output buffers and
incorporates input and output registers on–board with high speed SRAM.
The MCM69D536 allows the user to concurrently perform reads, writes, or
pass–through cycles in combination on the two data ports. The two address ports
(AX, AY) determine the read or write locations for their respective data ports
(DQX, DQY).
R,
The synchronous design allows for precise cycle control with the use of an
TO
external single clock (K). All signal pins except output enables (GX, GY) are
UC
registered on the rising edge of clock (K).
ND
The pass–through feature allows data to be passed from one port to the other,
O
X to
in either direction. The PTX input must be asserted to pass data from port
IC
port Y. The PTY will likewise pass data from port Y to port X. A pass–through
EM
S
operation takes precedence over a read operation.
E
followed. If
For the case when AX and AY are the same, certain protocols are
AL
and the other
both ports are read, the reads occur normally. If one port is
C
S
written
is read, the read from the array will occur before the data is written. If both ports
EE
are written, only the data on DQY will be written to the array.
R
•
•
•
•
•
Single 3.3 V
±
5% Power Supply
BY
Fast Access Times: 5 / 6 / 8 ns Max
ED
Throughput of 2.98 Gigabits/Second
IV
Single Clock Operation
H
E2,
Address, Data Input, E1,
C
PTX, PTY, WX, WY, and Data Output
R
Registers On–Chip
A
100 MHz Maximum Clock Frequency
Self–Timed Write
Two Bi–Directional Data Buses
Can be Configured as Separate I/O
Pass–Through Feature
Asynchronous Output Enables (GX, GY)
LVTTL Compatible I/O
Concurrent Reads and Writes
176–Pin TQFP Package
I
C.
N
TQ PACKAGE
176 LEAD TQFP
CASE 1101–01
F
•
•
•
•
•
•
•
•
•
Suggested Applications
— ATM
— Ethernet Switches
— Cell/Frame Buffers — SNA Switches
Product Family Configurations
Part
Number
MCM69D536
MCM69D618
MCM67Q709A
MCM67Q909
Dual
Address
Single
Address
Note 1
Note 1
— Routers
— Shared Memory
Dual
I/O
Separate
I/O
Note 2
Note 2
n
n
n
n
n
n
Configuration
32K x 36
64K x 18
128K x 9
512K x 9
VDD
3.3 V
3.3 V
5.0 V
5.0 V
n
n
NOTES:
1. Tie AX and AY address ports together for the part to function as a single address part.
2. Tie GX high for DQX to be inputs and tie WY high and GY low for DQY to be outputs.
REV 7
4/13/99
©
Motorola, Inc. 1999
MOTOROLA FAST SRAM
For More Information On This Product,
Go to: www.freescale.com
MCM69D536
1
Freescale Semiconductor, Inc.
PIN DESCRIPTIONS
Pin Locations
65, 63, 61, 59, 57, 55, 169, 167,
145, 143, 68, 70, 72, 74, 76
64, 62, 60, 58, 56, 54, 168, 166,
144, 142, 69, 71, 73, 75, 77
82, 86, 90, 94, 96, 100, 102, 106, 108,
113. 115, 119, 121, 125, 127, 131,
135, 139, 170, 174, 2, 6, 8, 12, 14, 18,
20, 25, 27, 31, 33, 37, 39, 43, 47, 51
83, 87, 91, 95, 97, 101, 103, 107, 109,
112, 114, 118, 120, 124, 126, 130, 134,
138, 171, 175, 3, 7, 9, 13, 15, 19, 21,
24, 26, 30, 32, 36, 38, 42, 46, 50
150
151
Symbol
AX0 –
AX14
AY0 –
AY14
DQX0 –
DQX35
Type
Input
Input
I/O
Description
Address Port X: Never allow floating addresses for inputs AX0 – AX14.
A pullup resistor is needed.
Address Port Y: Never allow floating addresses for inputs AY0 – AY14.
A pullup resistor is needed.
Data Input/Output Port X.
DQY0 –
DQY35
I/O
Data Input/Output Port Y.
Freescale Semiconductor, Inc...
152
153
156
146
147
CH
AR
4, 10, 16, 22, 28, 34, 40, 49,
148
149
67, 84, 92, 98, 104, 110,
116, 122, 128, 137, 155, 172
ED
IV
,I
E1
Input
Synchronous Chip Enable: Active
OR
low.
T
high.
E2
Input
Synchronous Chip Enable: Active
UC
D
GX
Input
Asynchronous Output Enable Port X Input:
N
buffers (DQXx pins).
Low — enables output
CO
high impedance.
High — DQXx
I
M
pins are
GY
Input
Asynchronous Output Enable Port Y Input:
SE
Low — enables output buffers (DQYx pins).
LE
High — DQYx pins are high impedance.
CA
K
Input
ES
Clock: This signal registers the address, data in, and all control signals
E
except G.
R
F
Input Pass–Through Port X.
PTX
Y
B
PTY
Input
Pass–Through Port Y.
WX
WY
VDD
Input
Input
Supply
Synchronous Write Enable Port X.
Synchronous Write Enable Port Y.
+ 3.3 V Power Supply.
C.
N
5, 11, 17, 23, 29, 35, 41, 48, 66,
85, 93, 99, 105, 111, 117, 123,
129, 136, 154, 173
1, 44, 45, 52, 53, 88, 89, 132,
133, 165, 176
78 – 81, 140, 141, 157 – 164
VSS
Supply
Ground.
VSS
NC
Supply
—
Bonded to die flag. No chip current flows through these pins.
No Connection: There is no connection to the chip.
MCM69D536
4
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
TRUTH TABLE
(See Notes 1 through 5)
Input at tn Clock
Operation Number
O
i N
b
1
2
3
4
5
6
7
8
E1
H
X
L
L
L
L
L
L
E2
X
L
H
H
H
H
H
H
WX
X
X
0
X
X
X
1
X
WY
X
X
X
0
X
X
X
1
PTX
X
X
X
X
0
X
1
1
PTY
X
X
X
X
X
0
1
Operation
Deselected
Deselected
Write X Port
Write Y Port
Pass–Through X to Y
Pass–Through Y to X
Freescale Semiconductor, Inc...
NOTES:
1. GX/GY must be controlled to avoid bus contention issues during write and pass–through cycles.
2. Operation numbers 3 – 6 can be used in any combination.
3. Operation numbers 4 and 7, 3 and 8, 7 and 8 can be combined.
4. Operation number 5 can not be combined with operation number 7 or 8 because pass–through takes precedence over a read operation.
5. Operation number 6 can not be combined with operation number 7 or 8 because pass–through takes precedence over a read operation.
tn
K
ADDRESS & CONTROL
DATA
ED
INPUT D
V
I
DATA OUTPUT Q
BY
EE
FR
LE
CA
S
VALID
S
CO
I
M
tn + 1
E
,I
OR
CT
DU
N
1
.
C
Read Y
N
Read X
PIPELINED READ ACCESS
VALID
CH
AR
PASS–THROUGH
VALID
ABSOLUTE MAXIMUM RATINGS
(See Note)
Rating
Power Supply Voltage
Voltage Relative to VSS for Any Pin
Except VDD
Output Current
Power Dissipation
Temperature Under Bias
Operating Temperature
Storage Temperature — Plastic
Symbol
VDD
Vin, Vout
Iout
PD
Tbias
TA
Tstg
Value
– 0.5 to 4.6
– 0.5 to VDD + 0.5
±
20
866
– 10 to 85
0 to 70
– 55 to 125
Unit
V
V
mA
mW
°C
°C
°C
This is a synchronous device. All synchro-
nous inputs must meet specified setup and hold
times with stable logic levels for
ALL
rising
edges of clock (K) while the device is selected.
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to these high–impedance
circuits.
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
MOTOROLA FAST SRAM
For More Information On This Product,
Go to: www.freescale.com
MCM69D536
5
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