ANV32AA3P
1Mb Quad SPI nvSRAM
FEATURES
• Compatible with Serial Peripheral Interface (SPI)
• Supports SPI Modes 0 and 3
• Interface options with Single SPI, Dual SPI and
Quad SPI
• Interface options separately controlled for
Instruction, Address and Data
• Modes: Standard, Burst and XIP
• 108 MHz clock rate
• Block Write Protection
• Write Disable Instruction for Software Data Pro-
tection
• WRITE and Secure WRITE
• READ, fast READ and Secure READ
• 16 Byte User Serial Number
• Configuration and Status Register
• Low Power Hibernate (HIB <3µA) Mode
• Unlimited READ / WRITE Endurance
• Automatic Non-volatile STORE on Power Down
• Non-Volatile STORE under Instruction and HSB
Control
• Automatic RECALL to SRAM on Power-Up
• Unlimited RECALL Cycles
• 100k STORE Cycles
• 100-Year Non-volatile Data Retention
• 2.7V to 3.6V main Power Supply
• 1.65V to 1.95V I/O Power Supply
• Commercial and Industrial Temperatures
• 24 Ball BGA Package (6 x 8)
• RoHS-Compliant
DESCRIPTION
The Anvo-Systems Dresden ANV32AA3P is a 1Mb
Quad SPI SRAM with a non-volatile SONOS storage
element included with each memory cell, organized as
128k words of 8 bits each. The devices are accessed
by a high speed Quad SPI-compatible bus. There are
different SPI options available: SPI, DPI and QPI. Addi-
tionally, in single SPI mode the address bytes and/or
the data byte(s) can be clocked in using dual or quad
interface. The ANV32AA3P is enabled through the
Chip Enable pin (E), accessed via serial clock (CLK)
and 3 operation modes either with single serial data
input (SI) and single serial data output (SO) or dual by
2 bidirectional input / outputs (I/O0 and I/O1) or quad
by 4 bidirectional inputs / outputs (I/O0, I/O1, I/O2, I/
O3).
The Quad SRAM interface provides the fast access &
cycle times, ease of use and unlimited READ & WRITE
endurance of a standard SRAM. Dedicated safety fea-
tures support high data accuracy.
With Secure WRITE operation the ANV32AA3P
accepts address and data only when the correct 2 Byte
CRC, generated from the complete 3 address Bytes
and 128 Byte data, has been transmitted. Corrupt data
cannot overwrite existing memory content and even
valid data would not overwrite on a corrupted address.
With configuration register bit 4 the success of the
Secure WRITE operation can be monitored. In case of
corrupt data, bit 4 will be set volatile to high.
With Secure READ operation the ANV32AA3P calcu-
lates the correct 2 Byte CRC parallel to data transfer.
The 2 Byte CRC is transmitted after 128 Bytes of data
have been read out.
Data transfer automatically to the non-volatile storage
cells when power loss is detected or in any brown out
situation (the PowerSTORE operation). On power-up,
data are automatically restored to the SRAM (the
Power-Up RECALL operation). The PowerSTORE
operation can be disabled via Configuration Register
settings.
Both STORE and RECALL operations are also avail-
able under instruction control, STORE can also be
hardware controlled via HSB pin.
BLOCK WRITE Protection is enabled by programming
the status register with 1 of 14 options to protect blocks
of the memory.
A non-volatile register supports the option of a 8 Byte
user defined serial number. This register is under cus-
tomer control only.
Document Control Nr. 030
June, 2018
Rev 1.0
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Anvo-Systems Dresden
ANV32AA3P
BLOCK DIAGRAM
FLASH Array
1024 x 1024
STORE
Row Decoder
Store / Recall
Control
HSB
SRAM
Array
1024 x 1024
RECALL
Power
Control
V
CC
V
CCQ
V
CAP
User Serial Number
Column I/O
Column Decoder
Data I/O Register
Status Register
Configuration Register
Instruction
Decode
Control
Logic
Instruction
Register
E
SCK
HOLD (I/O3)
SI (I/O0)
SO (I/O1)
WP (I/O2)
Address Counter / Decoder
PIN CONFIGURATION
1
2
3
4
5
PIN DESCRIPTIONS
Signal Name
E
Signal Description
Chip Enable
Serial Clock
Serial Input (SPI Mode)
SI or I/O0
I/O [0] in dual or quad mode
Serial Output (SPI Mode)
I/O [1] in dual or quad mode
Hold (Suspends Serial Input)
I/O [3] in quad mode
Write Protect
I/O [2] in quad mode
Hardware Store busy
Main Power Supply Voltage
I/O Power Supply Voltage
Capacitor Voltage
Ground
A
B
C
D
E
nc
SCK
HSB
nc
nc
nc
SCK
VSS
VCC
nc
nc
E
nc
WP
(I/O2)
SO or I/O1
nc
VCAP
SO
(I/O1)
SI
(I/O0)
HOLD
(I/O3)
HOLD or I/O3
nc
nc
nc
nc
VCCQ
nc
WP or I/O2
HSB
VCC
VCCQ
VCAP
VSS
BGA24 Top View
Serial Interface Description
Master:
The device that generates the serial clock.
Slave:
Because the Serial Clock pin (SCK) is always
an input, the device always operates as a slave.
Transmitter/Receiver:
The device has bi-directional
pins (SI, I/O0, SO, I/O1, HOLD, I/O3, WP, I/O2 and
HSB) designated for data transmission and reception.
In SPI and DPI mode HOLD and WP act as inputs only.
Output:
The SO, I/O0, I/O1, I/O2 and I/O3 pins are
used in read cycles to transfer data out of the device
after the falling edge of Serial Clock.
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June, 2018
Rev 1.0
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Input:
The SI, I/O0, I/O1, I/O2 and I/O3 pins are used
to transfer data into the device. They receive instruc-
tions, addresses, and data. Data are latched on the
rising edge of the Serial Clock.
Serial Clock:
The SCK pin is used to synchronize the
communication between a master and the device.
Instructions, addresses, or data, present on the input
pin, are latched on the rising edge of the clock, while
data on the output pins are changed after the falling
edge of the clock input.
Anvo-Systems Dresden
ANV32AA3P
MSB:
The Most Significant Bit (MSB) is the first bit
transmitted and received.
Serial Op-Code:
After the device is selected with E
going low, the first byte will be received. This byte
contains the op-code that defines the operations to be
performed.
Invalid Op-Code:
If an invalid op-code is received, no
data will be shifted into the device, and the output pins
will remain in a high impedance state until the falling
edge of E is detected. This will reinitialize the serial
communication.
Chip Enable:
The device is selected when the E pin is
low. When the device is not selected (E pin is high),
data will not be accepted via the input pins, and the
output pins will remain in a high impedance state.
Unless an internal WRITE cycle is in progress the
device will be in the Standby Mode. Driving Chip
Enable (E) Low enables the device, placing it in the
active power mode. After power-up a falling edge on
Chip Enable (E) is required prior to the start of any
instruction.
Write Protect:
The main purpose of this input signal is
to freeze the size of the area of memory that is pro-
tected against WRITE instructions (as specified by the
values in the BP2, BP1 and BP0 bits of the Status
Register) and the selected PowerSTORE mode. This
pin must be driven either High or Low, and must be
stable during all WRITE operations.
Hold:
The HOLD pin is used in conjunction with the E
pin to select the device. When the device is selected
and a serial sequence is underway, HOLD can be used
to pause the serial communication with the master
device without resetting the serial sequence.
HSB:
The HSB pin monitors a STORE operation in
progress when driving the pin Low (output). A Hard-
wareSTORE operation can be initiated by driving this
pin low (input).
Buffer Cap:
The VCAP pin provides the necessary
energy for the PowerSTORE operation, via an external
capacitor.
Connecting to the SPI Bus
These devices are fully compatible with the SPI pro-
tocol.
All instructions, addresses and input data bytes are
shifted in to the device most significant bit first. The
Serial Input (SI) is sampled on the first rising edge of
the Serial Clock (SCK) after Chip Enable (E) goes Low.
All output data bytes are shifted out after any read
instruction, most significant bit first. The Serial Output
(SO) is latched on the first falling edge of the Serial
Clock (SCK) after the instruction (such as the READ
from Memory Array, Secure READ and READ Status
Register instructions) has been clocked into the device.
The Figure shows four devices, connected to a MCU,
on an SPI bus. Only one device is selected at a time,
so only one device drives the Serial Data Output (SO)
line at a time, all the others being in high impedance.
SPI BUS Connection
HOLD - I/O3
WP - I/O2
SO - I/O1
SI - I/O0
SCK
E0
E1
E2
E3
HOLD - I/O3
WP - I/O2
SO - I/O1
SI - I/O0
SCK
E0
HSB
HOLD - I/O3
WP - I/O2
SO - I/O1
SI - I/O0
SCK
E1
HSB
HOLD - I/O3
WP - I/O2
SO - I/O1
SI - I/O0
SCK
E2
HSB
HOLD - I/O3
WP - I/O2
SO - I/O1
SI - I/O0
SCK
E3
HSB
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June, 2018
Rev 1.0
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Anvo-Systems Dresden
The HSB signal can be driven High or Low as appropriate (single or shared)
SPI / DPI / QPI
Master Controller
Slave:
ANV32AA3P
ANV32AA3P
SPI Modes
Each device can be driven by a microcontroller with its
SPI peripheral running in either of the following two
modes:
- Mode 0: CPOL=0, CPHA=0
- Mode 3: CPOL=1, CPHA=1
For these two modes, input data have been latched
with the rising edge of Serial Clock (SCK), and output
CPOL
0
1
CPHA
0
1
data is available from the falling edge of Serial Clock
(SCK). The difference between the two modes, as
shown for single SPI access in the following figure, is
the clock polarity when the bus master is in Stand-by
mode and not transferring data:
- SCK remains at 0 for (CPOL=0, CPHA=0)
- SCK remains at 1 for (CPOL=1, CPHA=1)
SCK
SCK
MSB
MSB
SI or I/O0
SO or I/O1
Dual and Quad I/O Modes
Beside the standard SPI interface, a command cont-
rolled reconfiguration of SI, SO (Dual Mode with I/O0
and I/O1), or SI, SO, HOLD and WP (Quad Mode with
I/O0, I/O1, I/O2 and I/O3) can be executed. In these
modes all READ operations will require dummy cycles
in contrast to WRITE operations which will require no
ones. Parallelism can be enabled for op-code, address
Mode Command
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
DPI
DPI
DPI
DPI
DPI
DPI
QPI
QPI
QPI
QPI
QPI
QPI
READ
S_READ
F_READ
FS_READ
DOR
DIOR
QOR
QIOR
WRITE
S_WRITE
DIW
DIOW
QIW
QIOW
READ
S_READ
F_READ
FS_READ
WRITE
S_WRITE
READ
S_READ
F_READ
FS_READ
WRITE
S_WRITE
and data or for address and data or just for data. READ
and WRITE operations can then be carried out in these
parallel modes. Secure READ, Secure F_READ and
Secure WRITE operations are available for SPI, DPI
and QPI Modes. There is a detailed description under
Functional Description later on.
DMY/
MB
cycles
0
0
8
8
8
4
8
4
0
0
0
0
0
0
1
1
4
4
0
0
1
1
2
2
0
0
Command input
SI
SI
SI
SI
I/O0
I/O0
I/O0
I/O0
SI
SI
I/O0
I/O0
I/O0
I/O0
I/O0, I/O1
I/O0, I/O1
I/O0, I/O1
I/O0, I/O1
I/O0, I/O1
I/O0, I/O1
I/O0, I/O1, I/O2, I/O3
I/O0, I/O1, I/O2, I/O3
I/O0, I/O1, I/O2, I/O3
I/O0, I/O1, I/O2, I/O3
I/O0, I/O1, I/O2, I/O3
I/O0, I/O1, I/O2, I/O3
Address input
SI
SI
SI
SI
I/O0
I/O0, I/O1
I/O0
I/O0, I/O1, I/O2, I/O3
SI
SI
I/O0
I/O0, I/O1
I/O0
I/O0, I/O1, I/O2, I/O3
I/O0, I/O1
I/O0, I/O1
I/O0, I/O1
I/O0, I/O1
I/O0, I/O1
I/O0, I/O1
I/O0, I/O1, I/O2, I/O3
I/O0, I/O1, I/O2, I/O3
I/O0, I/O1, I/O2, I/O3
I/O0, I/O1, I/O2, I/O3
I/O0, I/O1, I/O2, I/O3
I/O0, I/O1, I/O2, I/O3
Data input
Data output
SO
SO
SO
SO
I/O0, I/O1
I/O0, I/O1
I/O0, I/O1, I/O2, I/O3
I/O0, I/O1, I/O2, I/O3
SI
SI
I/O0, I/O1
I/O0, I/O1
I/O0, I/O1, I/O2, I/O3
I/O0, I/O1, I/O2, I/O3
I/O0, I/O1
I/O0, I/O1
I/O0, I/O1
I/O0, I/O1
I/O0, I/O1
I/O0, I/O1
I/O0, I/O1, I/O2, I/O3
I/O0, I/O1, I/O2, I/O3
I/O0, I/O1, I/O2, I/O3
I/O0, I/O1, I/O2, I/O3
I/O0, I/O1, I/O2, I/O3
I/O0, I/O1, I/O2, I/O3
Document Control Nr. 030
June, 2018
Rev 1.0
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Anvo-Systems Dresden
ANV32AA3P
Operating Features
Power-up:
When the power supply is turned on from V
SS
, Chip
Enable (E) has to follow the V
CC
voltage in accordance
with the definition of V
IH
. It must not be allowed to float,
but could be connected via a suitable pull-up resistor to
V
CC
. The Chip Enable signal (E) is edge as well as
level sensitive. This ensures that the device becomes
deselected after Power-down until E reaches V
CC
and
a falling edge of E from the V
IH
level has been detected
thereafter. This will start the first operation.
Power-on Reset:
In order to prevent data corruption and inadvertent
Write operations during power-up, all input signals will
be ignored and Data Output will be in high impedance
state. Power On Reset is completed when V
CC
reaches a stable V
CCmin
. Logical signals can be
applied.
Power-down / Brown Out:
When V
CC
drops during normal operation below
V
SWITCH
all external operations will be disabled, the
device will ignore any input signals and Data Output
will be in high impedance state. Power-down during
self timed STORE operation will not corrupt data in the
memory. WRITE operation of the current Byte will be
completed independent from the power supply. Prior to
any STORE operation the whole data in the non-vola-
tile memory will be erased to allow STORE operation of
new and restore of unchanged data.
Operating and Stand-by Modes:
When Chip Enable (E) is Low, the device is enabled. In
Operating Mode it is consuming I
CC(OP)
. In the other
case, when Chip Enable (E) is High without prior Hiber-
nate instruction, the device is in Standby Mode with the
reduced Supply Current I
SB
, with prior Hibernate
instruction the Supply Current will be with I
SBH
extreme
low. To exit the Hibernate Mode Chip Enable (E) has to
go Low and after t
RESTORE
all operations can be
executed.
Hold Condition:
The Hold (HOLD) signal suspends any serial commu-
nication with the device without resetting the clock
sequence.
Data Outputs are in high impedance state during Hold
condition, HOLD=Low. The other SPI-inputs are
disabled and Don’t Care.
The device has to be active with Chip Enable (E) Low
to enter the Hold condition. The device has to be
selected for the duration of the Hold condition, for the
selected operation to be continued after exiting the
Hold condition. The Hold condition starts when Hold
(HOLD) becomes Low, the device is active with Chip
Enable (E) Low and Serial Clock (SCK) is already Low.
The Hold conditions ends when Hold (HOLD) goes
High, the device is still active with Chip Enable (E) Low
and Serial Clock (SCK) is Low.
Chip Enable (E) has priority over Hold (HOLD). Driving
Chip Enable (E) High during Hold condition will reset
the device. With the next falling edge of Chip Select (E)
a new instruction has to be submitted.
Functional Description
The device utilizes an 8-bit instruction register. The list
of instructions and their operation codes are contained
in the following table. All instructions, addresses, and
data are transferred with the MSB first and start with a
high-to-low E transition. Each instruction starts with
one of the single-byte codes below. All instructions can
be set and executed with clock up to 108 MHz, beside
READ operations from the memory array (66 MHz).
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June, 2018
Rev 1.0
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Anvo-Systems Dresden
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