Anvo-Systems Dresden
FEATURES
• compatible with Serial Peripheral Interface (SPI)
• Supports SPI Modes 0 and 3
• 66MHz clock rate
• Block Write Protection
• Write Disable Instruction for Software Data Pro-
tection
• Secure WRITE
• Secure READ
• Hibernate Mode for low Standby Current
• Unlimited Read/Write Endurance
• Automatic Non-volatile STORE on Power Down
• Non-Volatile STORE under Instruction Control
• Automatic RECALL to SRAM on Power Up
• Unlimited RECALL Cycles
• 100k STORE Cycles
• 100-Year Non-volatile Data Retention
• Wide range 2.7V to 3.6V Power Supply
• Commercial and Industrial Temperatures
• 8-pin 150 mil SOIC and DFN Packages
• RoHS-Compliant
ANV32C91W
512kb Serial SPI nvSRAM
ANV32C91WC91W is enabled through the Chip
Enable pin (E) and accessed via a 3-wire interface con-
sisting of Serial Data Input (SI), Serial Data Output
(SO) and Serial Clock (SCK). All programming cycles
are self-timed, and no separate ERASE cycle is
required before STORE.
The serial SRAM provides the fast access & cycle
times, ease of use and unlimited read & write endur-
ance of a normal SRAM. Dedicated safety features
supporting high data accuracy.
With Secure WRITE operation the ANV32C91W
accepts address and data only when the correct 2 Byte
CRC, generated from the 16 bit address and 64 Byte
data, is transmitted. Corrupt data can not overwrite
existing memory content and even valid data would not
overwrite on a corrupted address. With status register
bit 4 the success of the WRITE operation can be moni-
tored. In case of corrupt data bit 4 will be set volatile to
high. With Secure READ operation the ANV32C91W
calculates the correct 2 Byte CRC parallel to data
transfer. The 2 Byte CRC is transmitted after 64 Bytes
of data have been transmitted.
Data transfers automatically to the non-volatile storage
cells when power loss is detected or in any brown out
situation (the PowerStore operation). On power up,
data is automatically restored to the SRAM (the Power
Up Recall operation).
Both STORE and RECALL operations are also avail-
able under instruction control.
BLOCK WRITE Protection is enabled by programming
the status register with one of four options to protect
blocks.
DESCRIPTION
The Anvo-Systems Dresden ANV32C91W is a 512kb
serial SRAM with a non-volatile SONOS storage ele-
ment included with each memory cell, organized as
64k words of 8 bits each. The devices are accessed by
a
high
speed
SPI-compatible
bus.
The
BLOCK DIAGRAM
FLASH Array
512 x 1024
STORE
R o w D ec o de r
Power
Control
V
CC
V
SS
SRAM
Array
512 x 1024
RECALL
Store/
Recall
Control
Column I/O
Column Decoder
Data IO Register
E
HOLD
Instruction Decode
Control Logic
Instruction Register
SO
SI
Address Counter / Decoder
SCK
This product conforms to Anvo-Systems Dresden specifi-
cations
Document Control Nr. 009
1
September, 2017
Rev 2.7
ANV32C91W
PIN CONFIGURATION
PIN DESCRIPTIONS
Signal Name
E
SCK
SI
SO
Top View
HOLD
VCC
VCAP
VSS
Signal Description
Chip Enable
Serial Clock
Serial Input
Serial Output
Hold (Suspends Serial
Input)
Power Supply Voltage
Capacitor Voltage
Ground
E
SO
VCAP
VSS
1
SOP/
DFN
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
8-pin SOP 150 mil or DFN
Serial Interface Description
Master:
The device that generates the serial clock.
Slave:
Because the Serial Clock pin (SCK) is always
an input, the device always operates as a slave.
Transmitter/Receiver:
The device has separate pins
designated for data transmission (SO) and reception
(SI).
Serial Output:
The SO pin is used to transfer data
serially out of the device. During a read cycle data is
shifted out on this pin after the falling edge of the Serial
Clock.
Serial Input:
The SI pin is used to transfer data serially
into the device. It receives instructions, addresses, and
data. Data is latched on the rising edge of the Serial
Clock.
Serial Clock:
The SCK pin is used to synchronize the
communication between a master and the device.
Instructions, addresses, or data, present on the SI pin,
are latched on the rising edge of the clock input, while
data on the SO pin is changed after the falling edge of
the clock input.
MSB:
The Most Significant Bit (MSB) is the first bit
transmitted and received.
Serial Op-Code:
After the device is selected with E
going low, the first byte will be received. This byte
contains the op-code that defines the operations to be
performed.
Invalid Op-Code:
If an invalid op-code is received, no
data will be shifted into the device, and the serial output
Document Control Nr. 009
September, 2017
Rev 2.7
2
pin (SO) will remain in a high impedance state until the
falling edge of E is detected. This will re-initialize the
serial communication.
Chip Enable:
The device is selected when the E pin is
low. When the device is not selected (E pin is high),
data will not be accepted via the SI pin, and the serial
output pin (SO) will remain in a high impedance state.
Unless an internal Write cycle is in progress the device
will be in the Standby mode. Driving Chip Enable (E)
Low enables the device, placing it in the active power
mode. After Power-up a falling edge on Chip Enable
(E) is required prior to the start of any instruction.
Write Protect:
The main purpose of this input signal is
to freeze the size of the area of memory that is pro-
tected against Write instructions (as specified by the
values in the BP1 and BP0 bits of the Status Register)
and the selected PowerStore mode. This pin must be
driven either High or Low, and must be stable during all
write operations. In case the Write Protect pin is not
available the part cannot be hardware protected (inter-
nal high).
Hold:
The HOLD pin is used in conjunction with the E
pin to select the device. When the device is selected
and a serial sequence is underway, HOLD can be used
to pause the serial communication with the master
device without resetting the serial sequence.
Buffer Cap:
The VCAP pin provides the necessary
energy for the PowerStore operation, via an external
capacitor.
Connecting to the SPI Bus
These devices are fully compatible with the SPI pro-
tocol.
All instructions, addresses and input data bytes are
Anvo-Systems Dresden
ANV32C91W
shifted in to the device most significant bit first. The
Serial Input (SI) is sampled on the first rising edge of
the Serial Clock (SCK) after Chip Enable (E) goes Low.
All output data bytes are shifted out after any read
instruction, most significant bit first. The Serial Output
(SO) is latched on the first falling edge of the Serial
Clock (SCK) after the instruction (such as the Read
from Memory Array, Secure Read and Read Status
Register instructions) has been clocked into the device.
The Figure shows four devices, connected to an MCU,
on an SPI bus. Only one device is selected at a time,
so only one device drives the Serial Data Output (SO)
line at a time, all the others being in high impedance.
SPI BUS CONNECTION
Master: Microcontroller
Data Out
Data In
Serial Clock
CS0
CS1
CS2
CS3
Slave: ANV32C91W
SI
SO
SCK
E
SI
SO
SCK
E
SI
SO
SCK
E
SI
SO
SCK
E
HOLD
The Hold (HOLD) signal should be
driven High or Low as appropriate.
HOLD
HOLD
HOLD
SPI Modes
Each device can be driven by a microcontroller with its
SPI peripheral running in either of the following two
modes:
- Mode 0: CPOL=0, CPHA=0
- Mode 3: CPOL=1, CPHA=1
For these two modes, input data is latched in on the
rising edge of Serial Clock (SCK), and output data is
available from the falling edge of Serial Clock (SCK).
The difference between the two modes, as shown in
the following figure, is the clock polarity when the bus
master is in Stand-by mode and not transferring data:
- SCK remains at 0 for (CPOL=0, CPHA=0)
- SCK remains at 1 for (CPOL=1, CPHA=1)
CPOL
0
1
CPHA
0
1
SCK
SCK
SI
SO
MSB
MSB
Document Control Nr. 009
September, 2017
Rev 2.7
3
Anvo-Systems Dresden
ANV32C91W
Operating Features
Power up:
When the power supply is turned on from
V
SS
, Chip Enable (E) has to follow the V
CC
voltage in
accordance with the definition of V
IH
. It must not be
allowed to float, but could be connected via a suitable
pull-up resistor to V
CC
.
The Chip Enable signal (E) is edge as well as level
sensitive. This ensures that the device becomes dese-
lected after Power-down until E reaches V
CC
and a fal-
ling edge of E from the V
IH
level has been detected
thereafter. This will start the first operation.
Power On Reset:
In order to prevent data corruption
and inadvertent Write operations during Power-up, all
input signals will be ignored and Serial Data Output
(SO) will be in high impedance state. Power On Reset
is exited when V
CC
reaches a stable V
CCmin
. Logical
signals can applied.
Power-down / Brown Out:
When V
CC
drops during
normal operation below V
SWITCH
all external opera-
tions will be disabled, the device will ignore any input
signals and Serial Data Output (SO) will be in high
impedance state. Power-down during self timed Store
Operation will not corrupt data in the memory. Write
operation of the current Byte will be completed inde-
pendent from the power supply. Prior to any Store ope-
ration the whole data in the non-volatile memory will be
Functional Description
The device utilizes an 8-bit instruction register. The list
of instructions and their operation codes are contained
in the following table. All instructions, addresses, and
Instruction Name
WREN
WRDI
RDSR
WRSR
READ
SECURE READ
WRITE
SECURE WRITE
STORE
RECALL
WRSNR
RDSNR
Hibernate
Instruction format
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0001 0011
0000 0010
0001 0010
0000 1000
0000 1001
1100 0010
1100 0011
10111001
data are transferred with the MSB first and start with a
high-to-low E transition. Each instruction starts with
one of the single-byte codes below.
Operation
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Secure Read Data from Memory Array with CRC
Write Data to Memory Array
Secure WRITE Data to Memory Array with CRC
Store SRAM data non-volatile
Recall non-volatile data to SRAM
Write User Serial Number
Read User Serial Number
Enter Hibernate Mode
erased to allow Store operation of new and restore of
unchanged data.
Operating and Stand-by Modes:
When Chip Enable
(E) is Low, the device is enabled. In Operating Mode it
is consuming I
CC(OP)
. In the other case, when Chip
Enable (E) is High, the device is in Standby Mode with
the reduced Supply Current I
CC(SB)
.
Hold Condition:
The Hold (HOLD) signal suspends
any serial communication with the device without reset-
ting the clock sequence.
Serial Data Output is in high impedance state during
Hold condition, HOLD=Low . The other SPI-inputs are
disabled and Don’t Care.
The device has to be active with Chip Enable (E) Low
to enter the Hold condition. The device has to be
selected for the duration of the Hold condition, for the
selected operation to be continued after exiting the
Hold condition. The Hold condition starts when Hold
(HOLD) becomes Low, the device is active with Chip
Enable (E) Low and Serial Clock (SCK) is already Low.
The Hold conditions ends when Hold (HOLD) goes
High, the device is still active with Chip Enable (E) Low
and Serial Clock (SCK) is Low.
Chip Enable (E) has priority over Hold (HOLD). Driving
Chip Enable (E) High during Hold condition will reset
the device. With the next falling edge of Chip Select (E)
a new instruction has to be submitted.
Document Control Nr. 009
September, 2017
Rev 2.7
4
Anvo-Systems Dresden
ANV32C91W
Write Enable (WREN):
The device will power-up in the write disable state
when V
CC
is applied. Before any WRITE instruction is
accepted, the Write Enable Latch has to be set with the
WREN command.
As shown in the figure below, to send this instruction to
E
0 1 2 3 4 5 6 7
the device, Chip Enable (E) is driven Low, and the bits
of the instruction byte are shifted in on Serial Data
Input (SI). The device then enters a wait state, waiting
for the device to be deselected, by Chip Enable (E)
being driven High.
SCK
Instruction
SI
SO
0
0
0
0
0
1
1
0
High-Z
Write Disable (WRDI):
To protect the device against inadvertent writes, the
Write Disable instruction disables all WRITE modes.
The WRDI instruction is independent of the status of
the WP pin.
As shown in the figure below, to send this instruction to
the device, Chip Enable (E) is driven Low and the bits
of the instruction byte are shifted in, on Serial Data
Input (SI). The device then enters a wait state, waiting
for the device to be deselected, by Chip Enable (E)
being driven High.
E
The Write Enable Latch (WEN) bit can be reset by any
of the following events:
- Power-up
- WRDI instruction execution
- WRSR instruction completion
- WRITE instruction completion
- WRSNR instruction completion
- SECURE WRITE instruction completion
0 1 2 3 4 5 6 7
SCK
Instruction
SI
SO
Read Status Register (RDSR):
0
0
0
0
0
1
0
0
High-Z
The Read Status Register instruction provides access
to the status register. The READY/BUSY, PowerSto-
reDisable (PDIS) and Write Enable status of the device
can be determined by the RDSR instruction. Similarly,
the Block Write Protection bits and WPEN indicate the
E
extent of protection employed. These bits, besides
RDY and WEN, are set by using the WRSR instruction.
The SWM bit will be automatically set as result of an
corrupt volatile data transfer in Secure WRITE and can
just be reset to zero by a successful SECURE WRITE.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
Instruction
SI
SO
0
0
0
0
0
1
0
1
High-Z
Status Register Out
7 6 5 4 3 2 1 0
MSB
Document Control Nr. 009
September, 2017
Rev 2.7
5
Anvo-Systems Dresden
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