Anvo-Systems Dresden
FEATURES
• compatible with Serial Peripheral Interface (SPI)
• Supports SPI Modes 0 and 3
• 66MHz clock rate
• Block Write Protection
• Secure WRITE
• Secure READ
• 2-Byte User Serial Number
• Hibernate Mode for low Standby Current
• Page and block rollover options
• Unlimited Read/Write Endurance
• Automatic Non-volatile STORE on Power Down
• Non-Volatile STORE under Instruction Control
• Automatic RECALL to SRAM on Power Up
• Unlimited RECALL Cycles
• 100k STORE Cycles
• 100-Year Non-volatile Data Retention
• 2.7V to 3.6V Power Supply
• Commercial and Industrial Temperatures
• 8-pin 150 mil SOIC and DFN Packages
• RoHS-Compliant
ANV32E61W
64kb Serial SPI nvSRAM
DESCRIPTION
The Anvo-Systems Dresden ANV32E61W is a 64kb
serial SRAM with a non-volatile SONOS storage ele-
ment included with each memory cell, organized as 8k
words of 8 bits each. The devices are accessed by a
high speed SPI-compatible bus. The ANV32E61W is
enabled through the Chip Enable pin (E) and accessed
via a 3-wire interface consisting of Serial Data Input
(SI), Serial Data Output (SO) and Serial Clock (SCK).
All programming cycles are self-timed, and no separate
ERASE cycle is required before STORE.
The serial SRAM provides the fast access & cycle
times, ease of use and unlimited read & write endur-
ance of a normal SRAM. Dedicated safety features
supporting high data accuracy.
With Secure WRITE operation the ANV32E61W
accepts address and data only when the correct 2-Byte
CRC, generated from the 13 bit address and 32 Byte
data, is transmitted. Corrupt data cannot overwrite
existing memory content and even valid data would not
overwrite on a corrupted address. With status register
bit 4 the success of the WRITE operation can be moni-
tored. In case of corrupt data bit 4 will be set volatile to
high. With Secure READ operation the ANV32E61W
calculates the correct 2-Byte CRC parallel to data
transfer. The 2Byte CRC is transmitted after 32 Bytes
of data have been transmitted.
Data transfers automatically to the non-volatile storage
cells when power loss is detected or in any brown out
situation (the PowerStore operation). On power up,
data is automatically restored to the SRAM (the Power
Up Recall operation). .
Both STORE and RECALL operations are also avail-
able under instruction control.
BLOCK WRITE Protection is enabled by programming
the status register with one of four options to protect
blocks.
A 2-Byte non-volatile register supports the option of a
2-Byte user defined serial number. This register is
under customer control only.
Status register bit 5 will control page and block roll over
modes.
This product conforms to Anvo-Systems Dresden specifications
Document Control Nr. 011
1
September, 2018
Rev 5.6
Anvo-Systems Dresden
BLOCK DIAGRAM
FLASH Array
256 x 256
Store
Row Decoder
SRAM
Array
256 x 256
Recall
Store /
Recall
Control
Power
Control
ANV32E61W
V
CC
V
CAP
V
SS
Column I O
/
Data IO Register
Column Decoder
Instruction Decode
Control Logic
E
HOLD
SO
SI
SCK
Address Counter / Decoder
PIN CONFIGURATION
PIN DESCRIPTIONS
Signal Name
E
SCK
SI
SO
Signal Description
Chip Enable
Serial Clock
Serial Input
Serial Output
Hold (Suspends Serial
Input)
Power Supply Voltage
Capacitor Voltage
Ground
E
SO
VCAP
VSS
1
SOP/
DFN
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
Top View
HOLD
8-pin SOP 150 mil or DFN
VCC
VCAP
VSS
Serial Interface Description
Master:
The device that generates the serial clock.
Slave:
Because the Serial Clock pin (SCK) is always
an input, the device always operates as a slave.
Transmitter/Receiver:
The device has separate pins
designated for data transmission (SO) and reception
(SI).
Serial Output:
The SO pin is used to transfer data
serially out of the device. During a read cycle data is
shifted out on this pin after the falling edge of the Serial
Clock.
Serial Input:
The SI pin is used to transfer data serially
into the device. It receives instructions, addresses, and
data. Data is latched on the rising edge of the Serial
Clock.
Serial Clock:
The SCK pin is used to synchronize the
communication between a master and the device.
Instructions, addresses, or data, present on the SI pin,
are latched on the rising edge of the clock input, while
data on the SO pin is changed after the falling edge of
the clock input.
MSB:
The Most Significant Bit (MSB) is the first bit
transmitted and received.
Serial Op-Code:
After the device is selected with E
going low, the first byte will be received. This byte
contains the op-code that defines the operations to be
performed.
This product conforms to Anvo-Systems Dresden specifications
Document Control Nr. 011
2
September, 2018
Rev 5.6
ANV32E61W
Invalid Op-Code:
If an invalid op-code is received, no
data will be shifted into the device, and the serial output
pin (SO) will remain in a high impedance state until the
falling edge of E is detected. This will re-initialize the
serial communication.
Chip Enable:
The device is selected when the E pin is
low. When the device is not selected (E pin is high),
data will not be accepted via the SI pin, and the serial
output pin (SO) will remain in a high impedance state.
Unless an internal Write cycle is in progress the device
will be in the Standby mode. Driving Chip Enable (E)
Low enables the device, placing it in the active power
mode. After Power-up a falling edge on Chip Enable
(E) is required prior to the start of any instruction.
Write Protect:
The Write Protect pin is not available for
this part (internal high). Hardware protection is not pos-
sible.
Hold:
The HOLD pin is used in conjunction with the E
pin to select the device. When the device is selected
and a serial sequence is underway, HOLD can be used
to pause the serial communication with the master
device without resetting the serial sequence.
Buffer Cap:
The VCAP pin provides the necessary
energy for the PowerStore operation, via an external
capacitor.
Connecting to the SPI Bus
These devices are fully compatible with the SPI pro-
tocol.
All instructions, addresses and input data bytes are
shifted in to the device most significant bit first. The
Serial Input (SI) is sampled on the first rising edge of
the Serial Clock (SCK) after Chip Enable (E) goes Low.
All output data bytes are shifted out after any read
instruction, most significant bit first. The Serial Output
(SO) is latched on the first falling edge of the Serial
Clock (SCK) after the instruction (such as the Read
from Memory Array, Secure Read and Read Status
Register instructions) has been clocked into the device.
The Figure shows four devices, connected to an MCU,
on an SPI bus. Only one device is selected at a time,
so only one device drives the Serial Data Output (SO)
line at a time, all the others being in high impedance.
SPI BUS CONNECTION
Master: Microcontroller
Data Out
Data In
Serial Clock
CS0
CS1
CS2
CS3
SI
SO
SCK
E
SI
SO
SCK
E
HOLD
HOLD
Slave: ANV32E61W
SI
SO
SCK
E
HOLD
SI
SO
SCK
E
HOLD
The Hold (HOLD) signal should be dri-
ven High or Low as appropriate.
Document Control Nr. 011
September, 2018
Rev 5.6
3
Anvo-Systems Dresden
ANV32E61W
SPI Modes
Each device can be driven by a microcontroller with its
SPI peripheral running in either of the following two
modes:
- Mode 0: CPOL=0, CPHA=0
- Mode 3: CPOL=1, CPHA=1
For these two modes, input data is latched in on the
rising edge of Serial Clock (SCK), and output data is
available from the falling edge of Serial Clock (SCK).
The difference between the two modes, as shown in
the following figure, is the clock polarity when the bus
master is in Stand-by mode and not transferring data:
- SCK remains at 0 for (CPOL=0, CPHA=0)
- SCK remains at 1 for (CPOL=1, CPHA=1)
CPOL
0
1
CPHA
0
1
SCK
SCK
SI
SO
MSB
MSB
Operating Features
Power up:
When the power supply is turned on from V
SS
, Chip
Enable (E) has to follow the V
CC
voltage in accordance
with the definition of V
IH
. It must not be allowed to float,
but could be connected via a suitable pull-up resistor to
V
CC
.
The Chip Enable signal (E) is edge as well as level
sensitive. This ensures that the device becomes dese-
lected after Power-down until E reaches V
CC
and a fal-
ling edge of E from the V
IH
level has been detected
thereafter. This will start the first operation.
Power On Reset:
In order to prevent data corruption and inadvertent
Write operations during Power-up, all input signals will
be ignored and Serial Data Output (SO) will be in high
impedance state. Power On Reset is completed when
V
CC
reaches a stable V
CCmin
. Logical signals can be
applied.
Power-down / Brown Out:
When V
CC
drops during normal operation below
V
SWITCH
all external operations will be disabled, the
device will ignore any input signals and Serial Data
Output (SO) will be in high impedance state. Power-
down during self timed Store Operation will not corrupt
data in the memory. Write operation of the current Byte
will be completed independent from the power supply.
Prior to any Store operation the whole data in the non-
volatile memory will be erased to allow Store operation
of new and restore of unchanged data.
Operating and Stand-by Modes:
When Chip Enable (E) is Low, the device is enabled. In
Operating Mode it is consuming I
CC(OP)
. In the other
case, when Chip Enable (E) is High without prior Hiber-
nate instruction, the device is in Standby Mode with the
reduced Supply Current I
CC(SB)
and with prior Hiber-
nate instruction the Supply Current will be with I
CC(HM)
extreme low. To exit the Hibernate mode Chip Enable
(E) has to go Low and after t
RESTORE
operations can
be executed.
Hold Condition:
The Hold (HOLD) signal suspends any serial commu-
nication with the device without resetting the clock
sequence.
Serial Data Output is in high impedance state during
Hold condition, HOLD=Low . The other SPI-inputs are
disabled and Don’t Care.
The device has to be active with Chip Enable (E) Low
to enter the Hold condition. The device has to be
selected for the duration of the Hold condition, for the
selected operation to be continued after exiting the
Hold condition. The Hold condition starts when Hold
(HOLD) becomes Low, the device is active with Chip
Enable (E) Low and Serial Clock (SCK) is already Low.
The Hold conditions ends when Hold (HOLD) goes
High, the device is still active with Chip Enable (E) Low
and Serial Clock (SCK) is Low.
Chip Enable (E) has priority over Hold (HOLD). Driving
Chip Enable (E) High during Hold condition will reset
the device. With the next falling edge of Chip Select (E)
a new instruction has to be submitted.
Document Control Nr. 011
September, 2018
Rev 5.6
4
Anvo-Systems Dresden
ANV32E61W
Functional Description
The device utilizes an 8-bit instruction register. The list
of instructions and their operation codes are contained
in the following table. All instructions, addresses, and
Instruction Name
WREN
WRDI
RDSR
WRSR
READ
SECURE READ
WRITE
SECURE WRITE
STORE
RECALL
WRSNR
RDSNR
Hibernate
Instruction format
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0001 0011
0000 0010
0001 0010
0000 1000
0000 1001
1100 0010
1100 0011
1011 1001
data are transferred with the MSB first and start with a
high-to-low E transition. Each instruction starts with
one of the single-byte codes below.
Operation
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Secure Read Data from Memory Array with CRC
Write Data to Memory Array
Secure WRITE Data to Memory Array with CRC
Store SRAM data non-volatile
Recall non-volatile data to SRAM
WRITE User Serial Number
READ User Serial Number
Enter Hibernate Mode
Write Enable (WREN):
The device will power-up in the write disable state
when V
CC
is applied. Before any WRITE instruction is
accepted, the Write Enable Latch has to be set with the
WREN command.
As shown in the figure below, to send this instruction to
the device, Chip Enable (E) is driven Low, and the bits
of the instruction byte are shifted in on Serial Data
Input (SI). The device then enters a wait state, waiting
for the device to be deselected, by Chip Enable (E)
being driven High.
E
0 1 2 3 4 5 6 7
SCK
Instruction
SI
SO
0
0
0
0
0
1
1
0
High-Z
Write Disable (WRDI):
To protect the device against inadvertent writes, the
Write Disable instruction disables all WRITE modes.
The WRDI instruction is independent of the status of
the WP pin.
As shown in the figure below, to send this instruction to
the device, Chip Enable (E) is driven Low and the bits
of the instruction byte are shifted in, on Serial Data
Input (SI). The device then enters a wait state, waiting
for the device to be deselected, by Chip Enable (E)
being driven High.
The Write Enable Latch (WEN) bit can be reset by any
of the following events:
- Power-up
- WRDI instruction execution
- WRSR instruction completion
- WRITE instruction completion
- SECURE WRITE instruction completion
Document Control Nr. 011
September, 2018
Rev 5.6
5
Anvo-Systems Dresden
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
