IDTCV143
1-TO-4 DIFFERENTIAL CLOCK BUFFER
COMMERCIAL TEMPERATURE RANGE
1-TO-4 DIFFERENTIAL
CLOCK BUFFER
IDTCV143
FEATURES:
•
•
•
•
•
•
•
Compliant with Intel DB400 spec
Four differential clock pairs at 0.7V
50ps skew
50ps cycle-to-cycle jitter
Programmable Bandwidth
PLL bypass configurable
Available in SSOP package
DESCRIPTION:
The CV143 differential buffer is compliant with Intel DB400 specifications. It
is intended to distribute the SRC (serial reference clock) as a companion chip
to the main clock of the CK409, CK410/CK410M, CK410B , etc. PLL is off in
bypass mode and has no clock detect.
FUNCTIONAL BLOCK DIAGRAM
OE_INV
(1)
(1)
OE_1, OE_6
SRC_STOP
(1)
Output
Control
DIF_1
DIF_1#
P
WRDWN
SCL
SDA
DIF_2
SM Bus
Controller
Output
Buffer
DIF_5
DIF_5#
DIF_2#
PLL/BYPASS#
SRC_IN
DIF_6
SRC_IN#
DIV
HIGH_BW#
PLL
DIF_6#
NOTE:
1. See OE_INV table for active HIGH or active LOW.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
© 2005 Integrated Device Technology, Inc.
OCTOBER 2005
DSC-6739/17
IDTCV143
1-TO-4 DIFFERENTIAL CLOCK BUFFER
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
V
DD
SRC_IN
SRC_IN#
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
DDA
Description
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage GND - 0.5
Storage Temperature
Ambient Operating Temperature
Case Temperature
Input ESD Protection
Human Body Model
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Min
Max
4.6
4.6
+150
+70
+115
Unit
V
V
°C
°C
°C
V
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
V
DDA
V
SSA
IREF
OE_INV
V
DD
DIF_6
DIF_6#
OE_6
(1)
V
DDIN
T
STG
T
AMBIENT
T
CASE
ESD Prot
–65
0
2000
V
SS
V
DD
DIF_1
DIF_1#
(1)
OE_1
DIF_2
DIF_2#
DIF_5
DIF_5#
V
DD
HIGH_BW#
SRC_STOP
(1)
P
WRDWN (1)
V
DD
PLL/BPASS#
SCL
SDA
HIGH_BW# SELECTION
PLL BW
PLL Peaking
HIGH_BW# = 0
Min. Typ. Max.
2
3
4
—
1
3
HIGH_BW#=1
Min. Typ.
Max.
0.7
1
1.4
—
1
3
Unit
MHz
dB
NOTE:
1. See OE_INV table for active HIGH or active LOW.
SSOP
TOP VIEW
OE_INV
OE_1, OE_6
P
WRDWN
SRC_STOP
OE_INV = 0
Active HIGH
Active LOW
Active LOW
OE_INV = 1
Active LOW
Active HIGH
Active HIGH
OE FUNCTIONALITY [OE_INV = 0]
OE_1, OE_6 Pin
1
1
0
0
OE_1, OE_6 SMBus bit
1
0
1
0
DIF_1, DIF_6
Normal
Tristate
Tristate
Tristate
DIF_1#, DIF_6#
Normal
Tristate
Tristate
Tristate
OE FUNCTIONALITY [OE_INV = 1]
OE_1, OE_6 Pin
1
1
0
0
OE_1, OE_6 SMBus bit
1
0
1
0
DIF_1, DIF_6
Tristate
Tristate
Normal
Tristate
DIF_1#, DIF_6#
Tristate
Tristate
Normal
Tristate
2
IDTCV143
1-TO-4 DIFFERENTIAL CLOCK BUFFER
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Name
SRC_IN, SRC_IN#
DIF_[2:1], DIF_ [2:1]#
DIF_[6:5], DIF_ [6:5]#
OE_1, OE_6
(1)
PLL/Bypass#
SCL
SDA
P
WRDWN
SRC_STOP
HIGH_BW#
OE_INV
IREF
Type
IN, DIF
OUT, DIF
OUT, DIF
IN
IN
IN
I/O, Open Collector
IN
IN
IN
IN
IN
Pin #
2,3
6, 7, 9, 10
19, 20, 22, 23
8, 21
12
13
14
15
16
17
25
26
0.7V differential SRC input
0.7V differential clock output
0.7V differential clock output
3.3V LVTTL input for enabling differential outputs
1 = PLL mode, 0 = bypass, PLL OFF
SMBus clock
SMBus data
3.3V LVTTL power down (see OE_INV table)
SRC stop (see OE_INV table)
0 = HIGH BW, 1 = LOW BW (see HIGH_BW# Selection table)
See OE_INV table
Reference current for differential output
Description
NOTE:
1. OE_1 controls DIF_1/DIF_1#, and OE_6 controls DIF_6/DIF_6#.
SM PROTOCOL
INDEX BLOCK WRITE PROTOCOL
Bit
1
2-9
10
11-18
19
20-27
28
29-36
37
38-45
46
# of bits
1
8
1
8
1
8
1
8
1
8
1
From
Master
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Description
Start
DCh
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Byte count, N (0 is not valid)
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
:
Nth data byte
Acknowledge
Stop
INDEX BLOCK READ PROTOCOL
Master can stop reading any time by issuing the stop bit without waiting
until Nth byte (byte count bit30-37).
Bit
1
2-9
10
11-18
19
20
21-28
29
30-37
38
39-46
47
48-55
# of bits
1
8
1
8
1
1
8
1
8
1
8
1
8
From
Master
Master
Slave
Master
Slave
Master
Master
Slave
Slave
Master
Slave
Master
Slave
Description
Start
DCh
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Repeated Start
DDh
Ack (Acknowledge)
Byte count, N (block read back of N
bytes)
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
:
Ack (Acknowledge)
Nth data byte
Not acknowledge
Stop
Master
Slave
Master
INDEX BYTE WRITE
Setting bit[11:18] = starting address, bit[20:27] = 01h.
INDEX BYTE READ
Setting bit[11:18] = starting address. After reading back the first data byte,
master issues Stop bit.
3
IDTCV143
1-TO-4 DIFFERENTIAL CLOCK BUFFER
COMMERCIAL TEMPERATURE RANGE
CONTROL REGISTERS
BYTE 0
Bit
7
6
5
4
3
2
1
0
Output(s) Affected
PowerDown dirve mode
SRC_STOP# drive mode
Reserved
Reserved
Reserved
High_BW#
PLL/Bypass#
Reserved
Description/Function
0
Driven
Driven
1
Tri-state
Tri-state
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power On
0
0
0
0
0
1
1
1
Logically AND with HW pin
Logically AND with HW pin
High band width
Bypass
Low band width
PLL mode
BYTE 1
Bit
7
6
5
4
3
2
1
0
Output(s) Affected
Reserved
DIFF_6
DIFF_5
Reserved
Reserved
DIFF_2
DIFF_1
Reserved
Description/Function
Output Enable
Output Enable
0
Tristate
Tristate
1
Enable
Enable
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power On
1
1
1
1
1
1
1
1
Output Enable
Output Enable
Tristate
Tristate
Enable
Enable
BYTE 2
Bit
7
6
5
4
3
2
1
0
Output(s) Affected
Reserved
DIFF_6
DIFF_5
Reserved
Reserved
DIFF_2
DIFF_1
Reserved
Description/Function
Free Running with SRC_STOP#
Free Running with SRC_STOP#
0
Free
Free
1
stopped
stopped
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power On
0
0
0
0
0
0
0
0
Free Running with SRC_STOP#
Free Running with SRC_STOP#
Free
Free
stopped
stopped
BYTE 3
Bit
7
6
5
4
3
2
1
0
Output(s) Affected
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description / Function
0
1
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power On
4
IDTCV143
1-TO-4 DIFFERENTIAL CLOCK BUFFER
COMMERCIAL TEMPERATURE RANGE
BYTE 4
Bit
7
6
5
4
3
2
1
0
Output(s) Affected
Description / Function
Revision ID
Revision ID
Revision ID
Revision ID
Vendor ID
Vendor ID
Vendor ID
Vendor ID
0
1
Type
R
R
R
R
R
R
R
R
Power On
0
0
0
0
0
1
0
1
BYTE 62 = 30h
BYTE 63 = 14h
ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT
PARAMETERS
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= 0°C to +70°C, Supply Voltage: V
DD
= 3.3V ± 5%
Symbol
V
IH
V
IL
I
IH
I
IL1
I
IL2
L
PIN
C
IN
C
OUT
Parameter
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Input LOW Current
Pin Inductance
(2)
Input Capacitance
(2)
Logic inputs
Output pin capacitance
3.3V ± 5%
3.3V ± 5%
V
IN
= V
DD
V
IN
= 0V, inputs with no pull-up resistors
V
IN
= 0V, inputs with pull-up resistors
Test Conditions
Min.
2
V
SS
- 0.3
–5
–5
–200
—
—
—
Typ.
—
—
—
—
—
—
—
—
Max.
V
DD
+ 0.3
0.8
5
—
—
7
5
6
Unit
V
V
µA
µA
µA
nH
pF
5
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
