Anvo-Systems Dresden
FEATURES
• High-performance 256kb non-volatile SRAM
• 25ns Access Time
• 10ns Output Enable Access Time
• I
CC
= 10mA typ. at 25 ns Cycle Time
• I
CC
= 2mA typ. at 250 ns Cycle Time
• Read Last Successful Written Address
• Unlimited Read/Write Endurance
• Automatic non-volatile STORE on Power Down or
Brown Out (POWERSTORE)
• Non-volatile STORE under Soft Sequence or
Hardware (HSB) Control
• Automatic RECALL to SRAM on Power Up or after
Brown Out
• Unlimited RECALL Cycles
• 100k STORE Cycles
• 100-Year non-volatile Data Retention
• 2.7V to 3.6V Power Supply
• Commercial and Industrial Temperatures
• BGA48 (6x8)
• RoHS-Compliant
ANV22A88W
32k x 8 nvSRAM
words of 8 bits each. There are 2 separate modes of
operation: SRAM mode and non-volatile mode. In
SRAM mode, the memory operates as an ordinary
static RAM. In non-volatile operation mode, data is
transferred in parallel from SRAM to the SONOS
elements (STORE) or from all of them to SRAM
(RECALL). In non-volatile mode SRAM functions are
disabled.
The SRAM can be read and written an unlimited
number of times, while independent non-volatile data
resides in SONOS elements. Data transfers from the
SRAM to the SONOS elements take place
automatically upon power down or brown out situation
(POWERSTORE) using charge stored in a small exter-
nal capacitor.
Transfers from the SONOS elements to the SRAM
(RECALL) take place automatically on power up or
may be initiated under user control by a software
sequence. Internally, RECALL is a two step procedure.
First, the SRAM data is cleared and second, the non-
volatile information is transferred into the SRAM cells.
STORE cycles also may be initiated under user control
by a software sequence or by a single pin (HSB).
Once a STORE cycle is initiated, further input or output
are disabled until the cycle is completed.
The POWERTSTORE function can also be enabled or
disabled by a software sequence.
With Read Last Successful Written Address it is possi-
ble to read out the 2 byte of address for data were last
WRITE was successful.
DESCRIPTION
The Anvo-Systems Dresden ANV22A88W is a 256kb
SRAM with a non-volatile SONOS storage element
included with each memory cell, organized as 32k
BLOCK DIAGRAM
Power Control
FLASH Array
512 x 512
A6
V
CC
STORE
Row Decoder
A7
A8
A9
A10
A11
A12
A13
A14
V
CAP
SRAM Array
512 x 512
RECALL
STORE /
RECALL
Control
HSB
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A0
A1
Software Detect
Column I/O
Input Buffer
Column Decoder
A2
A3
A4
A5
G
E
W
This product conforms to Anvo-Systems Dresden specifi-
cations
1
Document Control Nr. 0012
June, 2015
A0 - A14
Rev 0.3
ANV22A88W
PIN CONFIGURATION
Top View
1
A
B
C
D
E
F
G
H
NC
NC
DQ0
2
G
NC
NC
3
A0
A3
A5
NC
4
A1
A4
A6
A7
NC
NC
A13
A10
5
A2
E
NC
6
PIN DESCRIPTIONS
Signal Name
NC
NC
DQ4
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
Capacitor Voltage
Hardware Controlled Store/Busy
A0 - A14
DQ0 - DQ7
E
G
W
V
CC
V
SS
V
CAP
HSB
VSS DQ1
DQ5 VCC
DQ6 VSS
NC
W
A11
DQ7
NC
NC
VCC DQ2 V
CAP
DQ3
NC
NC
NC
A14
HSB A12
A8
A9
Device Operation
The ANV22A88W has two separate modes of opera-
tion:
- SRAM mode and
- non-volatile mode.
The memory operates in SRAM mode as a standard
fast static RAM. Data is transferred in non-volatile
mode from SRAM to SONOS elements (STORE) or
from SONOS elements to SRAM (RECALL). In this
non-volatile mode SRAM functions are disabled.
STORE cycles may be initiated under user control via a
software sequence or HSB assertion and are also
automatically initiated when the power supply voltage
level of the chip falls below V
SWITCH
. RECALL opera-
tions are automatically initiated upon power up and
may also occur when the V
CC
rises above V
SWITCH
,
after a low power condition. RECALL cycles may also
be initiated by a software sequence.
Power On Reset
In order to prevent data corruption and inadvertent
WRITE operations during Power-up, all input signals
will be ignored and Data Outputs DQ0 - DQ7 will be in
high impedance state. Power On Reset is exited when
V
CC
reaches a stable V
CCmin
. Logical signals can
applied.
Power-down / Brown Out
When V
CC
drops during normal operation below
V
SWITCH
all external operations will be disabled, the
device will ignore any input signals and Data Outputs
(DQ) will be in high impedance state. Power-down
during self timed Store Operation will not corrupt data
in the memory. Write operation of the current Byte will
be completed independent from the power supply. Prior
to any STORE operation the whole data in the non-
volatile memory will be erased to allow STORE opera-
tion of new and restore of unchanged data.
Power up
When the power supply is turned on from V
SS
, Chip
Enable (E) has to follow the V
CC
voltage in accordance
with the definition of V
IH
. It must not be allowed to float,
but could be connected via a suitable pull-up resistor to
V
CC
.
The Chip Enable signal (E) is edge as well as level
sensitive. This ensures that the device becomes dese-
lected after Power-Down until V
CC
reaches V
CCmin
and
a falling edge of E from the V
IH
level has been detected
thereafter. This will start the first operation.
Operating and Stand-by Modes
When Chip Enable (E) is Low, the device is enabled. In
Operating Mode it is consuming I
CC(OP)
. In the other
case, when Chip Enable (E) is High, the device is in
Standby Mode with the reduced Supply Current
I
CC(SB)
.
SRAM READ
The ANV22A88W performs a READ cycle whenever E
and G are LOW and HSB and W are HIGH. The add-
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Anvo-Systems Dresden
ANV22A88W
ress specified on pins A0 - A14 determines which of
the 32768 data bytes will be accessed. When the
READ is initiated by an address transition, the outputs
will be valid after a delay of t
cR
. If the READ is initiated
by E or G, the outputs will be valid at t
a(E)
or at t
a(G)
,
whichever is later. The data outputs will repeatedly res-
pond to address changes within the t
cR
access time wit-
hout the need for transition on any control input pins,
and will remain valid until another address change or
until E or G is brought HIGH or W or HSB is brought
LOW.
tor. A normal high frequency bypass capacitor between
the power supply voltage V
CC
and V
SS
is expected.
In order to prevent unneeded STORE operations,
automatic STOREs as well as those initiated by exter-
nally driving HSB LOW will be ignored unless at least
one WRITE operation has taken place since the most
recent STORE cycle. Note that if HSB is driven LOW
via external circuitry and no WRITES have taken place,
the part will still be disabled until HSB is allowed to
return HIGH. Software initiated STORE cycles are per-
formed regardless of whether or not a WRITE opera-
tion has taken place.
POWERSTORE operation without the external capaci-
tor will damage the volatile and non-volatile content of
the memory.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
LOW and HSB is HIGH. The address inputs must be
stable prior to entering the WRITE cycle and must
remain stable until either E or W goes HIGH at the end
of the cycle. The data on pins DQ0 - 7 will be written
into the memory if it is valid t
su(D)
before the end of a W
controlled WRITE or t
su(D)
before the end of an E cont-
rolled WRITE.
It is recommended that G is kept HIGH during the
entire WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers t
dis(W)
after W goes LOW.
Automatic RECALL
During power up, an automatic RECALL takes place.
At a low power condition (V
CC
< V
SWITCH
) an internal
RECALL request may be latched. As soon as power
supply voltage exceeds the sense voltage of V
SWITCH
, a
requested RECALL cycle will automatically be initiated
and will take t
RESTORE
to complete.
If the ANV22A88W is in a WRITE state at the end of
power up RECALL, the recalled SRAM data will be
overwritten. To help avoid this situation, a 10 k resis-
tor should be connected between W or E and power
supply voltage V
CC
.
POWERSTORE
During normal operation, the ANV22A88W will draw
current from V
CC
and charge up a capacitor connected
to the V
CAP
pin. This stored charge will be used by the
chip to perform a single STORE operation. If the
voltage on the V
CC
pin drops below V
SWITCH
, the part
will automatically disconnect the V
CAP
pin and the
whole memory from V
CC
and initiate a STORE opera-
tion.
Figure 1 shows the proper connection of capacitors for
automatic STORE operation.
Software non-volatile STORE
The ANV22A88W software controlled STORE cycle is
initiated by executing sequential E clocked READ cyc-
les from six specific address locations. By relying on
READ cycles only, the ANV22A88W implements non-
volatile operation while remaining compatible with
standard 32K x 8 SRAMs. During the STORE cycle, an
erase of the previous non-volatile data is performed
first, followed by a parallel programming of all non-vola-
tile elements. Once a STORE cycle is initiated, further
inputs and outputs are disabled until the cycle is
completed.
Because a sequence of addresses is used for STORE
initiation, it is important that no other READ or WRITE
accesses intervene in the sequence or the sequence
will be aborted.
To initiate the STORE cycle the following READ
sequence must be performed:
1.
Read address
0E38 (hex) Valid READ
2.
Read address
31C7 (hex) Valid READ
3.
Read address
03E0 (hex) Valid READ
4.
Read address
3C1F (hex) Valid READ
5.
Read address
303F (hex) Valid READ
6.
Read address
0FC0 (hex) Initiate STORE
Once the sixth address in the sequence has been ente-
Power Supply
10kO
HSB
V
CC
V
SS
V
CAP
C
CAP
GND
Figure 1: POWERSTORE Operation
Schematic Diagram
Each ANV22A88W must have its own STORE capaci-
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Anvo-Systems Dresden
ANV22A88W
red, the STORE cycle will commence and the chip will
be disabled. It is important that READ cycles and not
WRITE cycles are used in the sequence, although it is
not necessary that G is LOW for the sequence to be
valid. After the t
STORE
cycle time has been fulfilled, the
SRAM will again be activated for READ and WRITE
operation.
HIGH when it is not being driven LOW. To decrease the
sensitivity of this signal to noise generated on the PC
board, it may optionally be pulled to power supply via
an external resistor with a value such that the
combined load of the resistor and all parallel chip con-
nections does not exceed I
HSBOL
at V
OL
(see Figure 1).
Only if HSB is to be connected to external circuits, an
external pull-up resistor should be used.
During any STORE operation, regardless of how it was
initiated, the ANV22A88W will continue to drive the
HSB pin LOW, releasing it only when the STORE is
complete.
Upon completion of a STORE operation, the part will
be disabled until HSB actually goes HIGH.
Hardware Protection
1.
2.
3.
4.
5.
6.
Read address
Read address
Read address
Read address
Read address
Read address
0E38
31C7
03E0
3C1F
303F
0C63
(hex)
(hex)
(hex)
(hex)
(hex)
(hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL
The ANV22A88W offers hardware protection against
inadvertent STORE operation during low voltage condi-
tions. When V
CC
< V
SWITCH
, all software or HSB ini-
tiated STORE operations will be inhibited.
Disabling Automatic STORES
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the non-volatile
information is transferred into the SRAM cells. The
RECALL operation in no way alters the data in the
SONOS cells. The non-volatile data can be recalled an
unlimited number of times.
If the POWERSTORE function is not required, this
feature can be disabled by a soft-sequence.
In this case it is important that no other READ or
WRITE accesses intervene in the sequence or the
sequence will be aborted.
To initiate POWERSTORE disable the following READ
sequence must be performed:
1.
Read address
0E38 (hex) Valid READ
2.
Read address
31C7 (hex) Valid READ
3.
Read address
03E0 (hex) Valid READ
4.
Read address
03C1 (hex) Valid READ
5.
Read address
303F (hex) Valid READ
6.
Read address
0B45 (hex) disabled
Once the sixth address in the sequence has been ente-
red, the internal register is set volatile to POWER-
STORE = disable. With a Software controlled non-
volatile STORE this register takes the status non-vola-
tile. It is not necessary that G is LOW for the sequence
to be valid.
Software non-volatile RECALL
A RECALL cycle is initiated with a sequence of E clok-
ked READ operations in a manner similar to the
STORE initiation. To initiate the RECALL cycle the
following sequence of READ operations must be per-
formed:
HSB non-volatile STORE
The hardware controlled STORE Busy pin (HSB) is
connected to an open drain circuit acting as both input
and output to perform two different functions. When dri-
ven LOW by the internal chip circuitry it indicates that a
STORE operation (initiated via any means) is in prog-
ress within the chip. When driven LOW by external
circuitry for longer than t
w(H)S
, the chip will conditionally
initiate a STORE operation after t
dis(H)S
.
READ and WRITE operations that are in progress
when HSB is driven LOW (either by internal or external
circuitry) will be allowed to complete before the STORE
operation is performed, in the following manner.
After HSB goes LOW, the part will continue normal
SRAM operation for t
dis(H)S
. During t
dis(H)S
, a transition
on any address or control signal will terminate SRAM
operation and cause the STORE to commence.
Note that if an SRAM WRITE is attempted after HSB
has been forced LOW, the WRITE will not occur and
the STORE operation will begin immediately.
HARDWARE-STORE-BUSY (HSB) is a high speed,
low drive capability bidirectional control line.
In order to allow a bank of ANV22A88Ws to perform
synchronized STORE functions, the HSB pin from a
number of chips may be connected together. Each chip
contains a small internal current source to pull HSB
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June, 2015
Rev 0.3
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Enabling Automatic Stores
If the POWERSTORE function is requested again an
activation via a Soft Sequence can occur,
To initiate POWERSTORE enable again the following
READ sequence must be performed:
1.
Read address
0E38 (hex) Valid READ
2.
Read address
31C7 (hex) Valid READ
3.
Read address
03E0 (hex) Valid READ
4.
Read address
3C1F (hex) Valid READ
5.
Read address
303F (hex) Valid READ
6.
Read address
0B46 (hex) enabled
Anvo-Systems Dresden
ANV22A88W
Once the sixth address in the sequence has been ente-
red, the internal reister is set volatile to POWER-
STORE = enable. With a Software controlled non-
volatile STORE this register takes the status non-vola-
tile. It is not necessary that G is LOW for the sequence
to be valid.
1.
2.
3.
4.
5.
6.
Read address
Read address
Read address
Read address
Read address
Read address
0E38
31C7
03E0
3C1F
303F
0D31
(hex)
(hex)
(hex)
(hex)
(hex)
(hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
READ Byte low
Read Last Successful Written Address
An internal register monitors continuously all WRITE
addresses. With each successful WRITE it will be set
to the address of this operation. It is a 2 byte register
which is volatile during normal operation. If POWER-
STORE is enabled it will be stored in case of power
down or brown out like any other data in the memory
array. After Power Up the content can be read out via a
soft sequence. With the first WRITE the register will be
overwritten volatile and with the first STORE operation
also non-volatile. With any RECALL also the volatile
content of the Read Last Successful Written Address
register will be cleared and set to the non-volatile con-
tent of the register.
To initiate read out Read Last Successful Written Add-
ress register the following READ sequence must be
performed:
1.
Read address
0E38 (hex) Valid READ
2.
Read address
31C7 (hex) Valid READ
3.
Read address
03E0 (hex) Valid READ
4.
Read address
3C1F (hex) Valid READ
5.
Read address
303F (hex) Valid READ
6.
Read address
0D32 (hex) READ Byte high
Byte high is the upper address and byte low the lower
part of the address.
Low Average Active Power
The ANV22A88W has been designed to draw
significantly less power when E is LOW (chip enabled)
but the access cycle time is longer than 25 ns.
When E is HIGH the chip consumes only standby cur-
rent.
The overall average current drawn by the part depends
on the following items:
1. CMOS or TTL input levels
2. the time during which the chip is disabled (E HIGH)
3. the cycle time for accesses (E LOW)
4. the ratio of READs to WRITEs
5. the operating temperature
6. the power supply voltage level
Document Control Nr. 012
June 2015
Rev 0.3
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Anvo-Systems Dresden
FPGA/CPLD
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