products are low capacitance dual bidirectional high-speed Electronic
Current Limiters (ECLs), constructed using MOSFET semiconductor technology, and designed to protect
against faults caused by short circuits, overvoltage transients and faults in battery cells, up to rated limits.
The TBU
®
high-speed protector placed in the system circuit will monitor the current with the MOSFET detec-
tion circuit triggering to provide an effective barrier behind which sensitive electronics will not be exposed to
large voltages or currents during transient events.
The TBU
®
device is provided in a surface mount DFN package and meets industry standard requirements
such as RoHS and Pb Free solder reflow profiles.
Line 1 I/O
1
3
Line 1 I/O
Line 2 I/O
6
4
Line 2 I/O
TBU
®
Device
Absolute Maximum Ratings (@ T
A
= 25 °C Unless Otherwise Noted)
Symbol
V
imp
V
rms
T
op
T
stg
Parameter
Peak impulse voltage withstand with duration less than 10 ms
Continuous A.C. RMS voltage
Operating temperature range
Storage temperature range
Maximum Ambient Temperature
Part Number
TBU-DF055-xxx-WH
TBU-DF085-xxx-WH
TBU-DF055-xxx-WH
TBU-DF085-xxx-WH
Value
550
850
250
425
-55 to +125
-65 to +150
+125
Unit
V
V
°C
°C
°C
T
amax
Electrical Characteristics (@ T
A
= 25 °C Unless Otherwise Noted)
Symbol
I
trigger
Parameter
Current required for the device to go from operating state to
protected state
V
imp
= 550 V
V
imp
= 550 V
V
imp
= 550 V
V
imp
= 850 V
V
imp
= 850 V
V
imp
= 850 V
I
trigger
(min.) = 50 mA
I
trigger
(min.) = 300 mA
I
trigger
(min.) = 500 mA
I
trigger
(min.) = 50 mA
I
trigger
(min.) = 300 mA
I
trigger
(min.) = 500 mA
Part Number
TBU-DFxxx-050-WH
TBU-DFxxx-300-WH
TBU-DFxxx-500-WH
TBU-DF055-050-WH
TBU-DF055-300-WH
TBU-DF055-500-WH
TBU-DF085-050-WH
TBU-DF085-300-WH
TBU-DF085-500-WH
Min.
50
300
500
12
6
5
23
15
12
1
0.5
16
125
50
Typ.
75
450
750
Max.
100
600
1000
26
14
13
38
26
25
+0.5
Unit
mA
R
device
Series resistance of
the TBU
®
device
Ω
R
match
t
block
I
Q
V
reset
R
th(j-a)
R
th(j-a)
Package resistance matching of the TBU
®
device #1 - TBU
®
device #2
Time for the device to go from normal operating state to protected state
Current through the triggered TBU
®
device with 50 Vdc circuit voltage
Voltage below which the triggered TBU
®
device will transition to normal operating state
Junction to ambient - FR4 using JESD51-3 board
Junction to ambient - FR4 using JESD51-7 board
12
20
Ω
µs
mA
V
°C/W
°C/W
Environmental Characteristics
Parameter
Moisture Sensitivity Level
ESD Classification (HBM)
Value
1
1B
WARNING Cancer and Reproductive Harm -
www.P65Warnings.ca.gov
*RoHS Directive 2015/863, Mar 31, 2015 and Annex.
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
TBU-DF Series - TBU
®
High-Speed Protectors
Reference Application
The TBU
®
devices are general use protectors used in a wide
variety of applications, including telecommunications, industrial
communications and automotive battery management systems.
The maximum voltage rating of the TBU
®
device should never
be exceeded. Where necessary, an OVP device should be
employed to limit the maximum voltage. A cost-effective protection
solution combines Bourns
®
TBU
®
protection devices with a pair
of Bourns
®
TISP
®
Overvoltage Protectors or MOVs. For band-
width sensitive applications, a Bourns
®
GDT may be substituted
for the MOV.
1
Line
Side
OVP
OVP
Basic TBU Operation
The TBU
®
device, constructed using MOSFET semiconductor
technology, placed in the system circuit will monitor the
current with the MOSFET detection circuit triggering to provide
an effective barrier behind which sensitive electronics are not
exposed to large voltages or currents during transient events.
When operated, the TBU
®
device will limit the current to less
than the I
trigger
value within the t
block
duration. If voltage
above V
reset
is continuously sustained, the TBU
®
device will
subsequently reduce the current to a quiescent current level
within a period of time that is dependent upon the applied
voltage.
After the surge, the TBU
®
device resets when the voltage
across the TBU
®
device falls to the V
reset
level. The TBU
®
device will automatically reset on lines which have no DC bias
or have DC bias below V
reset
(such as unpowered signal lines).
3
Load
6
4
TBU
®
Device
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
TBU-DF Series - TBU
®
High-Speed Protectors
3312 - 2 mm SMD Trimming Potentiometer
Performance Graphs
Typical V-I Characteristics
ITRIP
CURRENT
VRESET
Normalized Itrigger vs. Temperature
1.8
1.6
TYPICAL TRIGGER CURRENT
Normalized ITrigger
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-55
-35
VOLTAGE
-15
5
25
45
65
85
105
125
Temperature (°C)
Power Derating Curve
3.0
Multilayer JESD51-7 (2 TBU HSPs)
Single Layer (2 TBU
®
HSPs)
Multilayer JESD51-7 (1 TBU
®
HSP)
Single Layer (1 TBU
®
HSP)
®
Normalized Resistance vs. Temperature
2.5
Total Maximum Power (W)
2.5
2.0
1.5
1.0
0.5
0.0
25
2.0
Normalized Resistance
1.5
1.0
0.5
0.0
-55
45
65
85
105
125
145
-35
-15
5
25
45
65
85
105
125
Junction Temperature (°C)
Temperature (°C)
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
TBU-DF Series - TBU
®
High-Speed Protectors
Product Dimensions
TOP VIEW
B
SIDE VIEW 2
D
K
G
L
A
4
5
6
J
XXXXX
YWWLL
PIN 1 INDICATOR
SIDE VIEW 1
C
E
F
3
2
1
I
H
CHAMFERED
CORNER
FOR PIN 1
IDENTIFICATION
0.25 ± 0.25
(.010 ± .010)
MM
DIMENSIONS:
(INCHES)
Dim.
A
B
C
D
E
F
G
H
I
J
K
L
Min.
5.40
(.213)
6.40
(.252)
0.80
(.031)
0.00
(.000)
1.90
(.075)
1.75
(.069)
0.65
(.026)
0.70
(.028)
0.30
(.012)
0.25
(.010)
0.75
(.030)
Nom.
5.50
(.217)
6.50
(.256)
0.90
(.035)
--
0.20
REF.
(.008)
.......F
2.00
(.079)
1.85
(.073)
0.70
(.028)
0.80
(.031)
0.35
(.014)
0.30
(.012)
0.80
(.031)
Max.
5.60
(.220)
6.60
(.260)
1.00
(.039)
0.05
(.002)
Pad #
1
2
3
4
5
6
Pin Out
Line 1 In/Out
NU (Not Used)
Line 1 In/Out
L
Line 2 In/Outt
NU (Not Used)
Line 2 In/Out
NOTES:
2.10
(.083)
1.95
(.077)
0.75
(.030)
0.90
(.035)
0.40
(.016)
0.35
(.014)
0.85
(.033)
1.
Pin 1 Indicator is laser marked; radius and location within the
Pin 2 and 5 are NU (Not Used) and must be left unconnected;
do not connect to In/Out lines, do not connect to system Ground.
Coplanarity on exposed pads shall not exceed 0.08 mm / (.003 in.).
Warpage shall not exceed 0.10 mm / (.004 in.) on all surfaces.
Exposed tie bars at package side are not plated.
2.
3.
4.
5.
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
TBU-DF Series - TBU
®
High-Speed Protectors
Recommended Pad Layout
TBU
®
High-Speed Protectors have a 100 % matte-tin termination
finish. For improved thermal dissipation, the recommended layout
uses PCB copper areas which extend beyond the exposed solder
pad. The exposed solder pads should be defined by a solder mask
which matches the pad layout of the TBU
®
device in size and spac-
K
ing. It is recommended that they should be the same dimension as
K
J
the TBU
®
pads but if smaller solder pads are used, they should be
E
F
C
®
centered on the TBU
B
package terminal pads and not more than
0.10-0.12 mm (0.004-0.005 in.) smaller in overall width or length.
1
Solder pad areas should not be larger than the TBU
®
3
pad sizes
2
to ensure adequate clearance is maintained. The recommended
A
stencil thickness is 0.10-0.12 mm (0.004-0.005 in.) with a stencil
opening size 0.025 mm (0.0010 in.) less than the solder pad size.
Extended copper areas beyond the solder pad significantly improve
the junction to
PIN 1
ambient thermal resistance, resulting in operation
D
at lower junction temperatures with a corresponding benefit of reli-
ability. All pads should soldered to the
SIDE VIEW
PCB, including pads
BOTTOM VIEW
marked
TOP VIEW
as NC or NU but no electrical connection should be made to these
pads. Care should be taken to assure no resistive path exists
between the NC or NU pins to any other point to avoid
Reflow Profile
Profile Feature
Average Ramp-Up Rate (Tsmax to Tp)
Preheat
- Temperature Min. (Tsmin)
- Temperature Max. (Tsmax)
- Time (tsmin to tsmax)
Pb-Free Assembly
3 °C/sec. max.
150 °C
200 °C
60-180 sec.
217 °C
60-150 sec.
260 °C
20-40 sec.
unexpected performance issues. For minimum parasitic
capacitance, it is recommended that signal, ground or power
signals are not routed beneath any pad. For minimum parasitic
capacitance, it is recommended that signal, ground or power
1.15
(.045)
signals are not routed beneath any pad.
0.70
J
E
N
(.028)
2.625
(.103)
H
3.55
(.140)
6
5
4
1
N
2
3
Dark grey areas show added PCB copper area for better
thermal resistance.
Time maintained above:
- Temperature (TL)
- Time (tL)
Peak/Classification Temperature (Tp)
Time within 5 °C of Actual Peak Temp. (tp)
Ramp-Down Rate
Time 25 °C to Peak Temperature
6 °C/sec. max.
8 min. max.
How to Order
Typical Part Marking
TBU - DF xxx - yyy - WH
TBU
®
Product
Series
DF = Dual Bidirectional Series
Impulse Voltage Rating
055 = 550 V
085 = 850 V
Trigger Current
050 = 50 mA
300 = 300 mA
500 = 500 mA
MANUFACTURER’S
TRADEMARK
XXXXX
YWWLL
PIN 1 INDICATOR
5 DIGIT PRODUCT CODE:
• 1ST ALPHA CHARACTER INDICATES PRODUCT FAMILY:
F = TBU-DF SERIES
• 2ND & 3RD DIGITS INDICATE IMPULSE VOLTAGE.
• 4TH & 5TH DIGITS INDICATE TRIGGER CURRENT.
Hold to Trip Ratio Suffix
W = Hold to Trip Ratio
Package Suffix
H = DFN Package
MANUFACTURING
DATE CODE:
• 1ST DIGIT INDICATES THE YEAR.
• 2ND & 3RD DIGITS INDICATE THE WEEK NUMBER.
• 4TH & 5TH DIGITS INDICATE LOT CODE.
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
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