Ultra Series
™
Crystal Oscillator
Si560 Data Sheet
Ultra Low Jitter Any-Frequency XO (90 fs), 0.2 to 3000 MHz
KEY FEATURES
The Si560 Ultra Series
™
oscillator utilizes Silicon Laboratories’ advanced 4
th
genera-
tion DSPLL
®
technology to provide an ultra-low jitter, low phase noise clock at any
output frequency. The device is factory-programmed to any frequency from 0.2 to
3000 MHz with <1 ppb resolution and maintains exceptionally low jitter for both inte-
ger and fractional frequencies across its operating range. The Si560 offers excellent
reliability and frequency stability as well as guaranteed aging performance. On-chip
power supply filtering provides industry-leading power supply noise rejection, simplify-
ing the task of generating low jitter clocks in noisy systems that use switched-mode
power supplies. Offered in industry-standard 3.2x5 mm and 5x7 mm footprints, the
Si560 has a dramatically simplified supply chain that enables Silicon Labs to ship cus-
tom frequency samples 1-2 weeks after receipt of order. Unlike a traditional XO,
where a different crystal is required for each output frequency, the Si560 uses one
simple crystal and a DSPLL IC-based approach to provide the desired output frequen-
cy. This process also guarantees 100% electrical testing of every device. The Si560 is
factory-configurable for a wide variety of user specifications, including frequency, out-
put format, and OE pin location/polarity. Specific configurations are factory-program-
med at time of shipment, eliminating the long lead times associated with custom oscil-
lators.
Pin Assignments
• Available with any frequency from 0.2
MHz to 3000 MHz
• Ultra low jitter: 90 fs RMS typical
(12 kHz – 20 MHz)
• Excellent PSRR and supply noise
immunity: –80 dBc Typ
• 20 ppm temp stability (–40 to 85 °C)
• 3.3 V, 2.5 V and 1.8 V V
DD
supply
operation from the same part number
• LVPECL, LVDS, CML, HCSL, CMOS,
and Dual CMOS output options
• 3.2x5, 5x7 mm package footprints
• Samples available with 1-2 week lead
times
APPLICATIONS
• 100G/200G/400G OTN, coherent optics
• 10G/40G/100G optical ethernet
• 56G/112G PAM4 clocking
• 3G-SDI/12G-SDI/24G-SDI broadcast
video
• Datacenter
• Test and measurement
• FPGA/ASIC clocking
OE/NC
1
2
3
(Top View)
6
5
4
VDD
CLK-
CLK+
NC/OE
GND
Pin #
1, 2
3
4
5
6
Descriptions
Selectable via ordering option
OE = Output enable; NC = No connect
GND = Ground
CLK+ = Clock output
NVM
Fixed
Frequency
Crystal
Frequency
Flexible
DSPLL
DCO
Low
Noise
Driver
OSC
Digital
Phase
Detector
Phase Error
Cancellation
Phase Error
Fractional
Divider
Digital
Loop
Filter
Flexible
Formats,
1.8V – 3.3V
Operation
CLK- = Complementary clock output. Not used for CMOS.
VDD = Power supply
Control
Power Supply Regulation
Output Enable
(Pin Control)
Built-in Power Supply
Noise Rejection
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Rev. 1.0
Si560 Data Sheet
Ordering Guide
1. Ordering Guide
The Si560 XO supports a variety of options including frequency, output format, and OE pin location/polarity, as shown in the chart
below. Specific device configurations are programmed into the part at time of shipment, and samples are available in 1-2 weeks. Silicon
Laboratories provides an online part number configuration utility to simplify this process. Refer to
www.silabs.com/oscillators
to access
this tool and for further ordering instructions.
XO Series
560
Description
Single Frequency
Temp Stability
A
Total Stability
2
±
20 ppm
±
50 ppm
A
B
Package
5x7 mm
3.2x5 mm
G
Temperature Grade
-40 to 85 °C
560
Signal Format
LVPECL
LVDS
CMOS
CML
HCSL
Dual CMOS
(In-Phase)
Dual CMOS
(Complementary)
Custom
1
VDD Range
2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
A
Order
Option
A
B
C
D
E
F
G
X
A
A
-
-
-
-
-
-
-
A
B
G
R
Device Revision
OE Pin
A
B
C
D
Pin 1
Pin 1
Pin 2
Pin 2
OE Polarity
Active High
Active Low
Active High
Active Low
R
<Blank>
Reel
Tape and Reel
Coil Tape
Frequency Code
3
Description
Mxxxxxx
F
CLK
< 1 MHz
xMxxxxx
1 MHz ≤ F
CLK
< 10 MHz
xxMxxxx
10 MHz ≤ F
CLK
< 100 MHz
xxxMxxx
100 MHz ≤ F
CLK
< 1000 MHz
1000 MHz ≤ F
CLK
≤ 3000 MHz
xxxxMxx
xxxxxx
Custom code if F
CLK
> 6 digits
Notes:
1. Contact Silicon Labs for non-standard configurations.
2. Total stability includes temp stability, initial accuracy, load pulling, VDD variation, and 20 year aging at 70 °C.
3. For example: 156.25 MHz = 156M250; 25 MHz = 25M0000. Create custom part numbers at
www.silabs.com/oscillators.
1.1 Technical Support
Frequently Asked Questions (FAQ)
Oscillator Phase Noise Lookup Utility
Quality and Reliability
Development Kits
www.silabs.com/Si560-FAQ
www.silabs.com/oscillator-phase-noise-lookup
www.silabs.com/quality
www.silabs.com/oscillator-tools
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Rev. 1.0 | 2
Si560 Data Sheet
Electrical Specifications
2. Electrical Specifications
Table 2.1. Electrical Specifications
V
DD
= 1.8 V, 2.5 or 3.3 V ± 5%, T
A
= –40 to 85 ºC
Parameter
Temperature Range
Frequency Range
Symbol
T
A
F
CLK
LVPECL, LVDS, CML
HCSL
CMOS, Dual CMOS
Supply Voltage
V
DD
3.3 V
2.5 V
1.8 V
Supply Current
I
DD
LVPECL (output enabled)
LVDS/CML (output enabled)
HCSL (output enabled)
CMOS (output enabled)
Dual CMOS (output enabled)
Tristate Hi-Z (output disabled)
Temperature Stability
Total Stability
1
Rise/Fall Time
(20% to 80% V
PP
)
F
STAB
T
R
/T
F
Frequency stability Grade A
Frequency stability Grade A
LVPECL/LVDS/CML
CMOS / Dual CMOS, (C
L
= 5 pF)
HCSL, F
CLK
>50 MHz
Duty Cycle
Output Enable (OE)
2
D
C
V
IH
V
IL
T
D
T
E
Powerup Time
LVPECL Output Option
3
t
OSC
V
OC
V
O
Output Disable Time, F
CLK
> 10 MHz
Output Enable Time, F
CLK
> 10 MHz
Time from 0.9 × V
DD
until output fre-
quency (F
CLK
) within spec
Mid-level
Swing (diff, F
CLK
< 1.5 GHz)
Swing (diff, F
CLK
> 1.5 GHz)
6
LVDS Output Option
4
V
OC
Mid-level (2.5 V, 3.3 V VDD)
Mid-level (1.8 V VDD)
V
O
Swing (diff, F
CLK
< 1.5 GHz)
Swing (diff, F
CLK
> 1.5 GHz)
6
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Test Condition/Comment
Min
–40
0.2
0.2
0.2
3.135
2.375
1.71
—
—
—
—
—
—
–20
–50
—
—
—
45
0.7 × V
DD
—
—
—
—
V
DD
– 1.42
1.1
0.55
1.125
0.8
0.5
0.25
Typ
—
—
—
—
3.3
2.5
1.8
110
90
85
85
95
73
—
—
—
0.5
—
—
—
—
—
—
—
—
—
—
1.20
0.9
0.7
0.5
Max
85
3000
400
250
3.465
2.625
1.89
160
157
130
135
145
—
20
50
350
1.5
550
55
—
0.3 × V
DD
3
20
10
V
DD
– 1.25
1.9
1.7
1.275
1.0
0.9
0.8
Unit
ºC
MHz
MHz
MHz
V
V
V
mA
mA
mA
mA
mA
mA
ppm
ppm
ps
ns
ps
%
V
V
µs
µs
ms
V
V
PP
V
PP
V
V
V
PP
V
PP
All formats
Rev. 1.0 | 3
Si560 Data Sheet
Electrical Specifications
Parameter
HCSL Output Option
5
Symbol
V
OH
V
OL
V
C
CML Output Option
(AC-Coupled)
CMOS Output Option
V
O
Test Condition/Comment
Output voltage high
Output voltage low
Crossing voltage
Swing (diff, F
CLK
≤ 1.5 GHz)
Swing (diff, F
CLK
> 1.5 GHz)
6
V
OH
V
OL
I
OH
= 8/6/4 mA for 3.3/2.5/1.8 V VDD
I
OL
= 8/6/4 mA for 3.3/2.5/1.8 V VDD
Min
660
–150
250
0.6
0.3
0.85 × V
DD
—
Typ
800
0
410
0.8
0.55
—
—
Max
850
150
550
1.0
0.9
—
0.15 × V
DD
Unit
mV
mV
mV
V
PP
V
PP
V
V
Notes:
1. Total Stability includes temperature stability, initial accuracy, load pulling, VDD variation, and aging for 20 yrs at 70 ºC.
2. OE includes a 50 kΩ pull-up to VDD for OE active high, or includes a 50 kΩ pull-down to GND for OE active low.
3. R
term
= 50 Ω to V
DD
– 2.0 V (see Figure 4.1).
4. R
term
= 100 Ω (differential) (see Figure 4.2).
5. R
term
= 50 Ω to GND (see Figure 4.2).
6. Refer to the figure below for Typical Clock Output Swing Amplitudes vs Frequency.
Figure 2.1. Typical Clock Output Swing Amplitudes vs. Frequency
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Rev. 1.0 | 4
Si560 Data Sheet
Electrical Specifications
Table 2.2. Clock Output Phase Jitter and PSRR
V
DD
= 1.8 V, 2.5 or 3.3 V ± 5%, T
A
= –40 to 85 ºC
Parameter
Phase Jitter (RMS, 12 kHz - 20 MHz)
1
All Differential Formats
Symbol
ϕJ
Test Condition/Comment
F
CLK
≥ 200 MHz
100 MHz ≤ F
CLK
< 200 MHz
LVPECL @ 156.25 MHz
Phase Jitter (RMS, 12 kHz - 20 MHz)
1
CMOS / Dual CMOS Formats
Spurs Induced by External Power Supply
Noise, 50 mVpp Ripple. LVDS 156.25 MHz
Output
ϕJ
PSRR
10 MHz ≤ F
CLK
< 250 MHz
100 kHz sine wave
200 kHz sine wave
500 kHz sine wave
1 MHz sine wave
Note:
1. Jitter inclusive of any spurs.
Table 2.3. 3.2 x 5 mm Clock Output Phase Noise (Typical)
Offset Frequency (f)
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
Offset Frequency (f)
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
156.25 MHz LVDS
–105
–129
–136
–142
–150
–159
–160
156.25 MHz
LVPECL
–109
–131
–135
–143
–150
–160
–161
200 MHz LVDS
–100
–126
–133
–140
–148
–161
–162
200 MHz
LVPECL
–102
–126
–134
–141
–148
–162
–163
644.53125 MHz LVDS
–92
–116
–125
–131
–138
–153
–154
644.53125 MHz
LVPECL
–92
–119
–124
–130
–138
–154
–155
dBc/Hz
Unit
dBc/Hz
Unit
Min
—
—
—
—
Typ
90
105
95
200
-83
-83
-82
-85
Max
140
160
125
—
Unit
fs
fs
fs
fs
dBc
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Rev. 1.0 | 5
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