Ultra Series
™
Crystal Oscillator
Si544 Data Sheet
Ultra Low Jitter I2C Programmable XO (150 fs), 0.2 to 1500 MHz
The Si544 Ultra Series
™
oscillator utilizes Silicon Laboratories’ advanced 4
th
generation DSPLL
®
technology to provide an ultra-low jitter, low phase noise
clock at any output frequency. The device is user-programmed via simple
I2C commands to provide any frequency from 0.2 to 1500 MHz with <1 ppb
resolution and maintains exceptionally low jitter for both integer and fraction-
al frequencies across its operating range. The Si544 offers excellent reliabili-
ty and frequency stability as well as guaranteed aging performance. On-chip
power supply filtering provides industry-leading power supply noise rejection,
simplifying the task of generating low jitter clocks in noisy systems that use
switched-mode power supplies. The Si544 has a dramatically simplified sup-
ply chain that enables Silicon Labs to ship custom frequency samples 1-2
weeks after receipt of order. Unlike a traditional XO, where a different crystal
is required for each output frequency, the Si544 uses one simple crystal and
a DSPLL IC-based approach to provide the desired output frequency. The
Si544 is factory-configurable for a wide variety of user specifications, includ-
ing startup frequency, I2C address, output format, and OE pin location/
polarity. Specific configurations are factory-programmed at time of shipment,
eliminating the long lead times associated with custom oscillators.
Pin Assignments
SDA
OE/FS/NC
1
7
6
VDD
KEY FEATURES
• I2C programmable to any frequency from 0.2 to
1500 MHz with < 1 ppb resolution
• Very low jitter: 150 fs Typ RMS (12 kHz – 20 MHz)
• Configure up to 4 pin-selectable startup frequencies
• I2C interface supports 100 kbps, 400 kbps, and 1
Mbps (Fast Mode Plus)
• Excellent PSRR and supply noise immunity: –80
dBc Typ
• 3.3 V, 2.5 V and 1.8 V V
DD
supply operation from
the same part number
• LVPECL, LVDS, CML, HCSL, CMOS, and Dual
CMOS output options
• 3.2x5, 5x7 mm package footprints
• Samples available with 1-2 week lead times
APPLICATIONS
• 100G/200G/400G OTN, coherent optics, PAM4
• 10G/40G/100G optical ethernet
• 3G-SDI/12G-SDI/24G-SDI broadcast video
• Servers, switches, storage, search acceleration
• Test and measurement
• FPGA/ASIC clocking
NC/OE/FS
GND
2
3
8
SCL
(Top View)
5
4
CLK–
CLK+
Pin #
1, 2
3
4
5
6
7
8
Descriptions
Selectable via ordering option
OE = Output enable; FS = Frequency Select; NC = No connect
GND = Ground
CLK+ = Clock output
CLK- = Complementary clock output. Not used for CMOS.
VDD = Power supply
SDA = I2C Serial Data
SCL = I2C Serial Clock
NVM
Control
OSC
Fixed
Frequency
Crystal
Frequency
Flexible
DSPLL
DCO
Low
Noise
Driver
Digital
Phase
Detector
Phase Error
Cancellation
Phase Error
Fractional
Divider
Digital
Loop
Filter
Flexible
Formats,
1.8V – 3.3V
Operation
Power Supply Regulation
OE, Frequency Select
(I2C and Pin Control)
Built-in Power Supply
Noise Rejection
silabs.com
| Building a more connected world.
Rev. 1.0
Si544 Data Sheet
Ordering Guide
1. Ordering Guide
The Si544 XO supports a variety of options including startup frequency, output format, and OE pin location/polarity, as shown in the
chart below. Specific device configurations are programmed into the part at time of shipment, and samples are available in 1-2 weeks.
Silicon Laboratories provides an online part number configuration utility to simplify this process. Refer to
www.silabs.com/oscillators
to
access this tool and for further ordering instructions.
XO Series
544
Description
I2C Oscillator
Temp Stability
±
20 ppm
±
10 ppm
±
7 ppm
Total Stability 2
±
50 ppm
±
25 ppm
±
20 ppm
Package
5x7 mm
3.2x5 mm
Temperature Grade
-40 to 85 °C
A
B
C
A
B
G
544
A
A
A
A
-
-
-
-
-
-
A
B
G
R
Device Revision
Signal Format
LVPECL
LVDS
CMOS
CML
HCSL
Dual CMOS
(In-Phase)
Dual CMOS
(Complementary)
Custom 1
VDD Range
2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
Order
Option
A
B
C
D
E
F
G
X
Code
A
B
C
D
E
F
G
H
J
Code
A
B
C
Supported Frequency Range
0.2-1500 MHz
0.2-800 MHz
0.2-325 MHz (CMOS available to 250 MHz)
Pinout Option
OE Pin
Pin 1
Pin 1
Pin 2
Pin 2
Pin 1
Pin 1
Pin 2
Pin 2
--
OE Polarity
Active High
Active Low
Active High
Active Low
Active High
Active Low
Active High
Active Low
--
FS0
(Dual)
--
--
--
--
Pin 2
Pin 2
Pin 1
Pin 1
Pin 1
FS1
(Quad)
--
--
--
--
--
--
--
--
Pin 2
Frequency
Code 3
Code
R
<Blank>
Reel
Tape and Reel
Coil Tape
Description
The Si544 supports one, two, or
four user-defined startup
frequencies in the range
selected by the Supported
Frequency Range code. A user-
defined 7-bit I2C address is
supported. Each unique startup
configuration and I2C address
combination is assigned a 6-digit
code.
xxxxxx
Single
Codes A, B
SDA
OE
NC
GND
1
2
3
8
SCL
Codes C, D
SDA
NC 1
OE 2
GND 3
8
SCL
If replacing Si570A-K, use Code C
If replacing Si570M-W, use Code D
7
6 VDD
5 CLK–
4 CLK+
FS0 1
OE 2
GND 3
7
6
5
4
VDD
CLK–
CLK+
OE
FS0
GND
Dual
Codes E, F
SDA
1
2
3
8
SCL
Codes G, H
SDA
7
6
5
8
SCL
4
VDD
CLK–
CLK+
7
6 VDD
5 CLK–
4 CLK+
FS0
FS1
GND
1
2
3
Quad
Code J
SDA
7
6
5
8
SCL
4
VDD
CLK–
CLK+
Notes:
1. Contact Silicon Labs for non-standard configurations.
2. Total stability includes temp stability, initial accuracy, load pulling, VDD variation, and 20 year aging at 70 °C.
3. Create custom part numbers at
www.silabs.com/oscillators.
silabs.com
| Building a more connected world.
Rev. 1.0 | 2
Si544 Data Sheet
Ordering Guide
1.1 Technical Support
Frequently Asked Questions (FAQ)
Oscillator Phase Noise Lookup Utility
Quality and Reliability
Development Kits
www.silabs.com/Si544-FAQ
www.silabs.com/oscillator-phase-noise-lookup
www.silabs.com/quality
www.silabs.com/oscillator-tools
silabs.com
| Building a more connected world.
Rev. 1.0 | 3
Si544 Data Sheet
Electrical Specifications
2. Electrical Specifications
Table 2.1. Electrical Specifications
V
DD
= 1.8 V, 2.5 or 3.3 V ± 5%, T
A
= –40 to 85 ºC
Parameter
Temperature Range
Frequency Range
Symbol
T
A
F
CLK
LVPECL, LVDS, CML
HCSL
CMOS, Dual CMOS
Supply Voltage
V
DD
3.3 V
2.5 V
1.8 V
Supply Current
I
DD
LVPECL (output enabled)
LVDS/CML (output enabled)
HCSL (output enabled)
CMOS (output enabled)
Dual CMOS (output enabled)
Tristate Hi-Z (output disabled)
Temperature Stability
Frequency stability Grade A
Frequency stability Grade B
Frequency stability Grade C
Total Stability
1
F
STAB
Frequency stability Grade A
Frequency stability Grade B
Frequency stability Grade C
Rise/Fall Time
(20% to 80% V
PP
)
T
R
/T
F
LVPECL/LVDS/CML
CMOS / Dual CMOS
(C
L
= 5 pF)
HCSL, F
CLK
>50 MHz
Duty Cycle
Output Enable (OE),
Frequency Select (FS0, FS1)
2
D
C
V
IH
V
IL
T
D
T
E
T
FS
Powerup Time
LVPECL Output Option
3
t
OSC
V
OC
V
O
silabs.com
| Building a more connected world.
Test Condition/Comment
Min
–40
0.2
0.2
0.2
3.135
2.375
1.71
—
—
—
—
—
—
–20
–10
–7
–50
–25
–20
—
—
—
45
0.7 × V
DD
—
Typ
—
—
—
—
3.3
2.5
1.8
100
75
80
74
80
64
—
—
—
—
—
—
—
0.5
—
—
—
—
—
—
—
—
—
—
Max
85
1500
400
250
3.465
2.625
1.89
132
111
125
108
125
100
20
10
7
50
25
20
350
1.5
550
55
—
0.3 × V
DD
3
20
10
10
V
DD
– 1.25
1.9
Unit
ºC
MHz
MHz
MHz
V
V
V
mA
mA
mA
mA
mA
mA
ppm
ppm
ppm
ppm
ppm
ppm
ps
ns
ps
%
V
V
µs
µs
ms
ms
V
V
PP
Rev. 1.0 | 4
All formats
Output Disable Time, F
CLK
>10 MHz
Output Enable Time, F
CLK
>10 MHz
Settling Time after FS Change
Time from 0.9 × V
DD
until output fre-
quency (F
CLK
) within spec
Mid-level
Swing (diff)
—
—
—
—
V
DD
– 1.42
1.1
Si544 Data Sheet
Electrical Specifications
Parameter
LVDS Output Option
4
Symbol
V
OC
Test Condition/Comment
Mid-level (2.5 V, 3.3 V VDD)
Mid-level (1.8 V VDD)
V
O
HCSL Output Option
5
V
OH
V
OL
V
C
CML Output Option (AC-Coupled)
CMOS Output Option
V
O
V
OH
V
OL
Swing (diff)
Output voltage high
Output voltage low
Crossing voltage
Swing (diff)
I
OH
= 8/6/4 mA for 3.3/2.5/1.8V VDD
I
OL
= 8/6/4 mA for 3.3/2.5/1.8V VDD
Min
1.125
0.8
0.5
660
–150
250
0.6
0.85 × V
DD
—
Typ
1.20
0.9
0.7
750
0
350
0.8
—
—
Max
1.275
1.0
0.9
850
150
550
1.0
—
0.15 × V
DD
Unit
V
V
V
PP
mV
mV
mV
V
PP
V
V
Notes:
1. Total Stability includes temperature stability, initial accuracy, load pulling, VDD variation, and aging for 20 yrs at 70 ºC.
2. OE includes a 50 kΩ pull-up to VDD for OE active high. Includes a 50 kΩ pull-down to GND for OE active low. FS0 and FS1 pins
each include a 50 kΩ pull-up to VDD. NC (No Connect) pins include a 50 kΩ pull-down to GND.
3. 50 Ω to V
DD
– 2.0 V.
4. R
term
= 100 Ω (differential).
5. 50 Ω to GND.
Table 2.2. I2C Characteristics
V
DD
= 1.8, 2.5, or 3.3 V ± 5%, T
A
= –40 to 85 ºC
Parameter
SDA, SCL Input Voltage High
SDA, SCL Input Voltage Low
Frequency Reprogramming Resolution
Frequency Range for Small Frequency
Change (Continuous Glitchless Output)
Settling Time for Small Frequency Change
Settling Time for Large Frequency Change
(Output Squelched during Frequency Transi-
tion)
Symbol
V
IH
V
IL
M
RES
From center frequency
< ±950 ppm from center fre-
quency
> ±950 ppm from center fre-
quency
Test Condition/Comment
Min
0.70 x
V
DD
—
—
-950
—
—
Typ
—
—
0.026
—
—
—
Max
—
0.30 x
V
DD
—
+950
100
10
Unit
V
V
ppb
ppm
μs
ms
silabs.com
| Building a more connected world.
Rev. 1.0 | 5
电源技术
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
