Ultra Series
™
Crystal Oscillator (VCXO)
Si569 Data Sheet
Ultra Low Jitter I2C Programmable VCXO (100 fs), 0.2 to
3000 MHz
The Si569 Ultra Series
™
voltage-controlled crystal oscillator utilizes Silicon
Laboratories’ advanced 4
th
generation DSPLL
®
technology to provide an ul-
tra-low jitter, low phase noise clock at any output frequency. The device is
user-programmed via simple I2C commands to provide any frequency from
0.2 to 3000 MHz with <1 ppb resolution and maintains exceptionally low jitter
for both integer and fractional frequencies across its operating range. On-
chip power supply filtering provides industry-leading power supply noise re-
jection, simplifying the task of generating low jitter clocks in noisy systems
that use switched-mode power supplies. Unlike a traditional XO, where a dif-
ferent crystal is required for each output frequency, the Si569 uses one sim-
ple crystal and a DSPLL IC-based approach to provide the desired output
frequency. The Si569 is factory-configurable for a wide variety of user speci-
fications, including startup frequency, I2C address, output format, and OE
pin location/polarity. Specific configurations are factory-programmed at time
of shipment, eliminating long lead times associated with custom oscillators.
Pin Assignments
SDA
VC
1
7
6
VDD
KEY FEATURES
• I2C programmable to any frequency from 0.2 to
3000 MHz with < 1 ppb resolution
• Ultra low jitter: 100 fs RMS Typ (12 kHz – 20 MHz)
• Configure up to 2 pin-selectable startup frequencies
• I2C interface supports 100 kbps, 400 kbps, and 1
Mbps (Fast Mode Plus)
• Excellent PSRR and supply noise immunity: –80
dBc Typ
• Programmable Kv (ppm/V) simplifies development
• 3.3 V, 2.5 V and 1.8 V V
DD
supply operation from
the same part number
• LVPECL, LVDS, CML, HCSL, CMOS, and Dual
CMOS output options
• 3.2x5, 5x7 mm package footprints
• Samples available with 1-2 week lead times
APPLICATIONS
• 100G/200G/400G OTN, coherent optics, PAM4
• 3G-SDI/12G-SDI/24G-SDI broadcast video
• Servers, switches, storage, search acceleration
• FPGA/ASIC clocking
OE/FS
GND
2
3
8
SCL
(Top View)
5
4
CLK–
CLK+
Pin #
1
2
3
4
5
6
7
8
VC = Voltage Control Pin
Descriptions
OSC
Fixed
Frequency
Crystal
Frequency
Flexible
DSPLL
DCO
Low
Noise
Driver
Selectable via ordering option
OE = Output enable; FS = Frequency Select
GND = Ground
CLK+ = Clock output
CLK- = Complementary clock output. Not used for CMOS.
VDD = Power supply
SDA = I2C Serial Data
SCL = I2C Serial Clock
Vc
ADC
Control
Digital
Phase
Detector
Phase Error
Cancellation
Phase Error
Fractional
Divider
Digital
Loop
Filter
Flexible
Formats,
1.8V – 3.3V
Operation
NVM
Power Supply Regulation
OE, Frequency Select
(I2C and Pin Control)
Built-in Power Supply
Noise Rejection
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Rev. 1.1
Si569 Data Sheet
Ordering Guide
1. Ordering Guide
The Si569 XO supports a variety of options including startup frequency, output format, and control voltage tuning slope, as shown in the
chart below. Specific device configurations are programmed into the part at time of shipment, and samples are available in 1-2 weeks.
Silicon Laboratories provides an online part number configuration utility to simplify this process. Refer to
www.silabs.com/oscillators
to
access this tool and for further ordering instructions.
VCXO Series
569
Description
I2C Programmable
Code
A
B
C
OE Pin
Pin 2
Pin 2
--
OE Polarity
Active High
Active Low
--
FS (Dual)
--
--
Pin 2
Package
5x7 mm
3.2x5 mm
Temperature Grade
G
-40 to 85 °C
A
B
569
A
A
A
A
-
-
-
-
-
-
A
B
G
R
Device Revision
Signal Format
LVPECL
LVDS
CMOS
CML
HCSL
Dual CMOS
(In-Phase)
Dual CMOS
(Complementary)
Custom
1
VDD Range
2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
Order
Option
A
B
C
D
E
F
G
X
A
B
C
D
E
F
Code
A
B
C
D
Supported Frequency Range
0.2-3000 MHz
0.2-1500 MHz
0.2-800 MHz
0.2-325 MHz (CMOS available to 250 MHz)
Frequency
Code
2
Code
R
<Blank>
Reel
Tape and Reel
Coil Tape
Temperature Stability =
±
20 ppm
3
Vc Tuning
Min APR (
±
ppm) at VDD
Slope
3.3V
2.5V
1.8V
Kv (ppm/V)
60
75
105
150
180
225
20
40
70
115
145
190
--
20
40
75
100
135
--
--
20
45
65
85
Description
The Si569 supports up to
two user-defined startup
frequencies in the range
selected by the Supported
Frequency Range code. A
user-defined 7-bit I2C
address is supported.
Each unique startup
configuration and I2C
address combination is
assigned a 6-digit code.
xxxxxx
Notes:
1. Contact Silicon Labs for non-standard configurations.
2. Create custom part numbers at
www.silabs.com/oscillators.
3. Min Absolute Pull Range (APR) includes temp stability, initial accuracy, load pulling, VDD variation, and 20 year aging at 70 °C.
a. For best jitter and phase noise performance, always choose the smallest Kv that meets the application’s minimum APR re-
quirements. Unlike SAW-based solutions which require higher Kv values to account for their higher temperature dependence,
the Si56x series provides lower Kv options to minimize noise coupling and jitter in real-world PLL designs.
b. Absolute Pull Range (APR) is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an APR of ±20
ppm is able to lock to a clock with a ±20 ppm stability over 20 years over all operating conditions.
c. APR (±) = (0.5 x VDD x tuning slope) - (initial accuracy + temp stability + load pulling + VDD variation + aging).
d. Minimum APR values noted above include absolute worst case values for all parameters.
e. See application note, "AN266:
VCXO Tuning Slope (Kv), Stability, and Absolute Pull Range (APR)"
for more information.
1.1 Technical Support
Frequently Asked Questions (FAQ)
Oscillator Phase Noise Lookup Utility
Quality and Reliability
Development Kits
www.silabs.com/Si569-FAQ
www.silabs.com/oscillator-phase-noise-lookup
www.silabs.com/quality
www.silabs.com/oscillator-tools
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Rev. 1.1 | 2
Si569 Data Sheet
Electrical Specifications
2. Electrical Specifications
Table 2.1. Electrical Specifications
V
DD
= 1.8 V, 2.5 or 3.3 V ± 5%, T
A
= –40 to 85 ºC
Parameter
Temperature Range
Frequency Range
Symbol
T
A
F
CLK
LVPECL, LVDS, CML
HCSL
CMOS, Dual CMOS
Supply Voltage
V
DD
3.3 V
2.5 V
1.8 V
Supply Current
I
DD
LVPECL (output enabled)
LVDS/CML (output enabled)
HCSL (output enabled)
CMOS (output enabled)
Dual CMOS (output enabled)
Tristate Hi-Z (output disabled)
Temperature Stability
1
Rise/Fall Time
(20% to 80% V
PP
)
T
R
/T
F
-40 to 85 °C
LVPECL/LVDS/CML
CMOS / Dual CMOS
(C
L
= 5 pF)
HCSL, F
CLK
>50 MHz
Duty Cycle
Output Enable (OE),
Frequency Select (FS)
2
D
C
V
IH
V
IL
T
D
T
E
T
FS
Powerup Time
LVPECL Output Option
3
t
OSC
V
OC
V
O
Output Disable Time, F
CLK
>10 MHz
Output Enable Time, F
CLK
>10 MHz
Settling Time after FS Change
Time from 0.9 × V
DD
until output fre-
quency (F
CLK
) within spec
Mid-level
Swing (diff, F
CLK
< 1.5 GHz)
Swing (diff, F
CLK
> 1.5 GHz)
6
All formats
Test Condition/Comment
Min
–40
0.2
0.2
0.2
3.135
2.375
1.71
—
—
—
—
—
—
–20
—
—
—
45
0.7 × V
DD
—
—
—
—
—
V
DD
– 1.42
1.1
0.55
Typ
—
—
—
—
3.3
2.5
1.8
120
100
95
95
105
83
—
—
0.5
—
—
—
—
—
—
—
—
—
—
—
Max
85
3000
400
250
3.465
2.625
1.89
170
167
140
145
155
—
20
350
1.5
450
55
—
0.3 × V
DD
3
20
10
10
V
DD
– 1.25
1.9
1.7
Unit
ºC
MHz
MHz
MHz
V
V
V
mA
mA
mA
mA
mA
mA
ppm
ps
ns
ps
%
V
V
µs
µs
ms
ms
V
V
PP
V
PP
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Rev. 1.1 | 3
Si569 Data Sheet
Electrical Specifications
Parameter
LVDS Output Option
4
Symbol
V
OC
Test Condition/Comment
Mid-level (2.5 V, 3.3 V VDD)
Mid-level (1.8 V VDD)
V
O
Swing (diff, F
CLK
< 1.5 GHz)
Swing (diff, F
CLK
> 1.5 GHz)
6
Swing (diff, F
CLK
< 1.6 GHz)
7
HCSL Output Option
5
V
OH
V
OL
V
C
CML Output Option (AC-Coupled)
V
O
Output voltage high
Output voltage low
Crossing voltage
Swing (diff, F
CLK
< 1.5 GHz)
Swing (diff, F
CLK
> 1.5 GHz)
6
CMOS Output Option
V
OH
V
OL
I
OH
= 8/6/4 mA for 3.3/2.5/1.8V VDD
I
OL
= 8/6/4 mA for 3.3/2.5/1.8V VDD
Min
1.125
0.8
0.5
0.25
0.6
660
–150
250
0.6
0.3
0.85 × V
DD
—
Typ
1.20
0.9
0.7
0.5
0.8
800
0
410
0.8
0.55
—
—
Max
1.275
1.0
0.9
0.8
1.0
850
150
550
1.0
0.9
—
0.15 × V
DD
Unit
V
V
V
PP
V
PP
V
PP
mV
mV
mV
V
PP
V
PP
V
V
Notes:
1. Min APR includes ±20 ppm temperature stability, initial accuracy, load pulling, VDD variation, and aging for 20 yrs at 70 ºC.
2. OE includes a 50 kΩ pull-up to VDD for OE active high, or includes a 50 kΩ pull-down to GND for OE active low. FS pin includes
a 50 kΩ pull-up to VDD.
3. R
term
= 50 Ω to V
DD
– 2.0 V (see Figure 4.1).
4. R
term
= 100 Ω (differential) (see Figure 4.2).
5. R
term
= 50 Ω to GND (see Figure 4.2).
6. Refer to the figure below for Typical Clock Output Swing Amplitudes vs Frequency.
7. High drive LVDS swing is supported when following the method shown in section
5.8 Configuring High Drive LVDS Swing.
Figure 2.1. Typical Clock Output Swing Amplitudes vs. Frequency
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Si569 Data Sheet
Electrical Specifications
Table 2.2. I2C Characteristics
V
DD
= 1.8, 2.5, or 3.3 V ± 5%, T
A
= –40 to 85 ºC
Parameter
SDA, SCL Input Voltage High
SDA, SCL Input Voltage Low
Frequency Reprogramming Resolution
Frequency Range for Small Frequency
Change (Continuous Glitchless Output)
Settling Time for Small Frequency Change
Settling Time for Large Frequency Change
(Output Squelched during Frequency Transi-
tion)
Symbol
V
IH
V
IL
M
RES
From center frequency
< ±950 ppm from center
frequency
> ±950 ppm from center
frequency
Test Condition/Comment
Min
0.70 x
V
DD
—
—
-950
—
—
Typ
—
—
0.004
—
—
—
Max
—
0.30 x
V
DD
—
+950
100
10
Unit
V
V
ppb
ppm
μs
ms
Table 2.3. V
C
Control Voltage Input
V
DD
= 1.8, 2.5 or 3.3 V ± 5%, T
A
= –40 to 85 ºC
Parameter
Control Voltage Range
Control Voltage Tuning Slope
(Vc = 10% VDD to 90% VDD)
Kv Variation
Control Voltage Linearity
Modulation Bandwidth
Vc Input Impedance
Symbol
V
C
Kv
Kv_var
LVC
BW
ZVC
Best Straight Line fit
Positive slope, ordering option
Test Condition
Min
0.1 x
VDD
Typ
VDD/2
Max
0.9 x
VDD
Unit
V
ppm/V
%
%
kHz
kΩ
60, 75, 105, 150, 180, 225
—
–1.5
—
500
—
±0.5
10
—
±10
+1.5
—
—
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