Ultra Series
™
Crystal Oscillator (VCXO)
Si565 Data Sheet
Ultra Low Jitter Any-Frequency VCXO (100 fs), 0.2 to 3000
MHz
The Si565 Ultra Series
™
voltage-controlled crystal oscillator utilizes Silicon Labo-
ratories’ advanced 4
th
generation DSPLL
®
technology to provide an ultra-low jit-
ter, low phase noise clock at any output frequency. The device is factory-pro-
grammed to any frequency from 0.2 to 3000 MHz with <1 ppb resolution and
maintains exceptionally low jitter for both integer and fractional frequencies
across its operating range. On-chip power supply filtering provides industry-lead-
ing power supply noise rejection, simplifying the task of generating low jitter
clocks in noisy systems that use switched-mode power supplies. Offered in in-
dustry-standard 3.2x5 mm and 5x7 mm footprints, the Si565 has a dramatically
simplified supply chain that enables Silicon Labs to ship custom frequency sam-
ples 1-2 weeks after receipt of order. Unlike a traditional XO, where a different
crystal is required for each output frequency, the Si565 uses one simple crystal
and a DSPLL IC-based approach to provide the desired output frequency. The
Si565 is factory-configurable for a wide variety of user specifications, including
frequency, output format, and OE pin location/polarity. Specific configurations are
factory-programmed at time of shipment, eliminating the long lead times associ-
ated with custom oscillators.
Pin Assignments
VC
1
6
VDD
KEY FEATURES
• Available with any frequency from 200 kHz to
3000 MHz
• Ultra low jitter: 100 fs RMS typical
(12 kHz – 20 MHz)
• Excellent PSRR and supply noise immunity:
–80 dBc Typ
• 3.3 V, 2.5 V and 1.8 V V
DD
supply operation
from the same part number
• LVPECL, LVDS, CML, HCSL, CMOS, and Dual
CMOS output options
• 3.2x5, 5x7 mm package footprints
• Samples available with 1-2 week lead times
APPLICATIONS
• 100G/200G/400G OTN, coherent optics
• 10G/25G/40G/100G Ethernet
• 56G/112G PAM4 clocking
• 3G-SDI/12G-SDI/24G-SDI broadcast video
• Servers, switches, storage, NICs, search
acceleration
• Test and measurement
• FPGA/ASIC clocking
OE
GND
2
3
5
4
CLK–
CLK+
(Top View)
Pin #
1
2
3
4
5
6
VC = Voltage Control Pin
Descriptions
OSC
Fixed
Frequency
Crystal
Frequency
Flexible
DSPLL
DCO
Low
Noise
Driver
OE = Output enable
GND = Ground
CLK+ = Clock output
CLK- = Complementary clock output. Not used for CMOS.
VDD = Power supply
Vc
ADC
Control
Digital
Phase
Detector
Phase Error
Cancellation
Phase Error
Fractional
Divider
Digital
Loop
Filter
Flexible
Formats,
1.8V – 3.3V
Operation
NVM
Power Supply Regulation
Output Enable
(Pin Control)
Built-in Power Supply
Noise Rejection
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Rev. 1.0
Si565 Data Sheet
Ordering Guide
1. Ordering Guide
The Si565 VCXO supports a variety of options including frequency, output format, and OE pin location/polarity, as shown in the chart
below. Specific device configurations are programmed into the part at time of shipment, and samples are available in 1-2 weeks. Silicon
Laboratories provides an online part number configuration utility to simplify this process. Refer to
www.silabs.com/oscillators
to access
this tool and for further ordering instructions.
VCXO Series
565
Description
Single Frequency VCXO
Code
A
B
OE Pin
Pin 2
Pin 2
OE Polarity
Active High
Active Low
A
B
Package
5x7 mm
3.2x5 mm
G
Temperature Grade
-40 to 85 °C
565
A
A
A
-
-
-
-
-
-
-
A
B
G
R
Device Revision
Order
Option
2.5, 3.3 V
A
1.8, 2.5, 3.3 V
B
VDD Range
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
C
D
E
F
G
X
A
B
C
D
E
F
Code
R
<Blank>
Frequency
Code
2
Mxxxxxx
xMxxxxx
xxMxxxx
xxxMxxx
xxxxMxx
xxxxxx
Reel
Tape and Reel
Coil Tape
Signal Format
LVPECL
LVDS
CMOS
CML
HCSL
Dual CMOS
(In-Phase)
Dual CMOS
(Complementary)
Custom
1
Temperature Stability =
±
20 ppm
3
Vc Tuning
Min APR [
±
ppm] at VDD
Slope
3.3V
2.5V
1.8V
Kv [ppm/V]
60
75
105
150
180
225
20
40
70
115
145
190
--
20
40
75
100
135
--
--
20
45
65
85
Description
F
CLK
< 1 MHz
1 MHz ≤ F
CLK
< 10 MHz
10 MHz ≤ F
CLK
< 100 MHz
100 MHz ≤ F
CLK
< 1000 MHz
1000 MHz ≤ F
CLK
< 3000 MHz
Custom code if F
CLK
> 6 digits
Notes:
1. Contact Silicon Labs for non-standard configurations.
2. Create custom part numbers at
www.silabs.com/oscillators.
3. Min Absolute Pull Range (APR) includes temp stability, initial accuracy, load pulling, VDD variation, and 20 year aging at 70 °C.
a. For best jitter and phase noise performance, always choose the smallest Kv that meets the application’s minimum APR re-
quirements. Unlike SAW-based solutions which require higher Kv values to account for their higher temperature dependence,
the Si56x series provides lower Kv options to minimize noise coupling and jitter in real-world PLL designs.
b. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an APR of ±20 ppm is able to lock to a
clock with a ±20 ppm stability over 20 years over all operating conditions.
c. APR (±) = (0.5 x VDD x tuning slope) - (initial accuracy + temp stability + load pulling + VDD variation + aging).
d. Minimum APR values noted above include absolute worst case values for all parameters.
e. See application note, "AN266:
VCXO Tuning Slope (Kv), Stability, and Absolute Pull Range (APR)"
for more information.
1.1 Technical Support
Frequently Asked Questions (FAQ)
Oscillator Phase Noise Lookup Utility
Quality and Reliability
Development Kits
www.silabs.com/Si565-FAQ
www.silabs.com/oscillator-phase-noise-lookup
www.silabs.com/quality
www.silabs.com/oscillator-tools
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Rev. 1.0 | 2
Si565 Data Sheet
Electrical Specifications
2. Electrical Specifications
Table 2.1. Electrical Specifications
V
DD
= 1.8 V, 2.5 or 3.3 V ± 5%, T
A
= –40 to 85 ºC
Parameter
Temperature Range
Frequency Range
Symbol
T
A
F
CLK
LVPECL, LVDS, CML
HCSL
CMOS, Dual CMOS
Supply Voltage
V
DD
3.3 V
2.5 V
1.8 V
Supply Current
I
DD
LVPECL (output enabled)
LVDS/CML (output enabled)
HCSL (output enabled)
CMOS (output enabled)
Dual CMOS (output enabled)
Tristate Hi-Z (output disabled)
Temperature Stability
1
Rise/Fall Time
(20% to 80% V
PP
)
T
R
/T
F
-40 to 85 °C
LVPECL/LVDS/CML
CMOS / Dual CMOS
(C
L
= 5 pF)
HCSL, F
CLK
> 50 MHz
Duty Cycle
Output Enable (OE)
2
D
C
V
IH
V
IL
T
D
T
E
Powerup Time
LVPECL Output Option
3
t
OSC
V
OC
V
O
Output Disable Time, F
CLK
> 10 MHz
Output Enable Time, F
CLK
> 10 MHz
Time from 0.9 × V
DD
until output fre-
quency (F
CLK
) within spec
Mid-level
Swing (diff, F
CLK
≤ 1.5 GHz)
Swing (diff, F
CLK
> 1.5 GHz)
6
LVDS Output Option
4
V
OC
Mid-level (2.5 V, 3.3 V VDD)
Mid-level (1.8 V VDD)
V
O
Swing (diff, F
CLK
≤ 1.5 GHz)
Swing (diff, F
CLK
> 1.5 GHz)
6
All formats
Test Condition/Comment
Min
–40
0.2
0.2
0.2
3.135
2.375
1.71
—
—
—
—
—
—
–20
—
—
—
45
0.7 × V
DD
—
—
—
—
V
DD
– 1.42
1.1
0.55
1.125
0.8
0.5
0.25
Typ
—
—
—
—
3.3
2.5
1.8
120
100
95
95
105
83
—
—
0.5
—
—
—
—
—
—
—
—
—
—
1.20
0.9
0.7
0.5
Max
85
3000
400
250
3.465
2.625
1.89
170
167
140
145
155
—
20
350
1.5
550
55
—
0.3 × V
DD
3
20
10
V
DD
– 1.25
1.9
1.7
1.275
1.0
0.9
0.8
Unit
ºC
MHz
MHz
MHz
V
V
V
mA
mA
mA
mA
mA
mA
ppm
ps
ns
ps
%
V
V
µs
µs
ms
V
V
PP
V
PP
V
V
V
PP
V
PP
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Rev. 1.0 | 3
Si565 Data Sheet
Electrical Specifications
Parameter
HCSL Output Option
5
Symbol
V
OH
V
OL
V
C
CML Output Option (AC-Coupled)
V
O
Test Condition/Comment
Output voltage high
Output voltage low
Crossing voltage
Swing (diff, F
CLK
≤ 1.5 GHz)
Swing (diff, F
CLK
> 1.5 GHz)
6
CMOS Output Option
V
OH
V
OL
I
OH
= 8/6/4 mA for 3.3/2.5/1.8 V VDD
I
OL
= 8/6/4 mA for 3.3/2.5/1.8 V VDD
Min
660
–150
250
0.6
0.3
0.85 × V
DD
—
Typ
800
0
410
0.8
0.55
—
—
Max
850
150
550
1.0
0.9
—
0.15 × V
DD
Unit
mV
mV
mV
V
PP
V
PP
V
V
Notes:
1. Min APR includes temperature stability, initial accuracy, load pulling, VDD variation, and aging for 20 yrs at 70 ºC.
2. OE includes a 50 kΩ pull-up to VDD for OE active high, or includes a 50 kΩ pull-down to GND for OE active low.
3. R
term
= 50 Ω to V
DD
– 2.0 V (see Figure 4.1).
4. R
term
= 100 Ω (differential) (see Figure 4.2).
5. R
term
= 50 Ω to GND (see Figure 4.2).
6. Refer to the figure below for Typical Clock Output Swing Amplitudes vs Frequency.
Figure 2.1. Typical Clock Output Swing Amplitudes vs. Frequency
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Si565 Data Sheet
Electrical Specifications
Table 2.2. V
C
Control Voltage Input
V
DD
= 1.8, 2.5 or 3.3 V ± 5%, T
A
= –40 to 85 ºC
Parameter
Control Voltage Range
Control Voltage Tuning Slope
(Vc = 10% VDD to 90% VDD)
Kv Variation
Control Voltage Linearity
Modulation Bandwidth
Vc Input Impedance
Symbol
V
C
Kv
Kv_var
LVC
BW
ZVC
Table 2.3. Clock Output Phase Jitter and PSRR
V
DD
= 1.8 V, 2.5 or 3.3 V ± 5%, T
A
= –40 to 85 ºC
Parameter
Phase Jitter (RMS, 12 kHz - 20 MHz)
1
All Differential Formats, F
CLK
≥ 200 MHz
Symbol
ϕJ
Test Condition/Comment
Kv = 60 ppm/V
Kv = 75 ppm/V
Kv = 105 ppm/V
Kv = 150 ppm/V
Kv = 180 ppm/V
Kv = 225 ppm/V
Phase Jitter (RMS, 12 kHz - 20 MHz)
1
All Diff Formats, 100 MHz ≤ F
CLK
< 200 MHz
ϕJ
Kv = 60 ppm/V
Kv = 75 ppm/V
Kv = 105 ppm/V
Kv = 150 ppm/V
Kv = 180 ppm/V
Kv = 225 ppm/V
Phase Jitter (RMS, 12 kHz - 20 MHz)
1
LVDS, F
CLK
= 156.25 MHz
ϕJ
Kv = 60 ppm/V
Kv = 75 ppm/V
Kv = 105 ppm/V
Kv = 150 ppm/V
Kv = 180 ppm/V
Kv = 225 ppm/V
Phase Jitter (RMS, 12 kHz - 20 MHz)
1
CMOS / Dual CMOS Formats
ϕJ
10 MHz ≤ F
CLK
< 250 MHz
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Typ
100
103
110
123
132
150
115
118
125
138
147
165
110
113
120
133
142
160
200
Max
150
—
—
—
—
—
170
—
—
—
—
—
130
—
—
—
—
—
—
Unit
fs
fs
fs
fs
fs
fs
fs
fs
fs
fs
fs
fs
fs
fs
fs
fs
fs
fs
fs
Best Straight Line fit
Positive slope, ordering option
Test Condition
Min
0.1 x
VDD
Typ
VDD/2
Max
0.9 x
VDD
Unit
V
ppm/V
%
%
kHz
kΩ
60, 75, 105, 150, 180, 225
—
–1.5
—
500
—
±0.5
10
—
±10
+1.5
—
—
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