MCP6S21/2/6/8
Single-Ended, Rail-to-Rail I/O, Low Gain PGA
Features
• Multiplexed Inputs: 1, 2, 6 or 8 channels
• 8 Gain Selections:
- +1, +2, +4, +5, +8, +10, +16 or +32 V/V
• Serial Peripheral Interface (SPI)
• Rail-to-Rail Input and Output
• Low Gain Error: ±1% (max)
• Low Offset: ±275 µV (max)
• High Bandwidth: 2 to 12 MHz (typ)
• Low Noise: 10 nV/Hz @ 10 kHz (typ)
• Low Supply Current: 1.0 mA (typ)
• Single Supply: 2.5V to 5.5V
Description
The Microchip Technology Inc. MCP6S21/2/6/8 are
analog Programmable Gain Amplifiers (PGA). They
can be configured for gains from +1 V/V to +32 V/V and
the input multiplexer can select one of up to eight chan-
nels through an SPI port. The serial interface can also
put the PGA into shutdown to conserve power. These
PGAs are optimized for high speed, low offset voltage
and single-supply operation with rail-to-rail input and
output capability. These specifications support single
supply applications needing flexible performance or
multiple inputs.
The one channel MCP6S21 and the two channel
MCP6S22 are available in 8-pin PDIP, SOIC and
MSOP packages. The six channel MCP6S26 is avail-
able in 14-pin PDIP, SOIC and TSSOP packages. The
eight channel MCP6S28 is available in 16-pin PDIP
and SOIC packages. All parts are fully specified from
-40°C to +85°C.
Typical Applications
•
•
•
•
•
•
A/D Converter Driver
Multiplexed Analog Applications
Data Acquisition
Industrial Instrumentation
Test Equipment
Medical Instrumentation
Block Diagram
V
DD
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CS
SI
SO
SCK
+
-
MUX
R
F
8
Gain
Switches
SPI™
Logic
R
G
V
OUT
Resistor Ladder (R
LAD
)
Package Types
MCP6S21
PDIP, SOIC, MSOP
V
OUT
1
CH0 2
V
REF
3
V
SS
4
8 V
DD
7 SCK
6 SI
5 CS
MCP6S22
PDIP, SOIC, MSOP
V
OUT
1
CH0 2
CH1 3
V
SS
4
8 V
DD
7 SCK
6 SI
5 CS
MCP6S26
PDIP, SOIC, TSSOP
V
OUT
1
CH0 2
CH1 3
CH2 4
CH3 5
CH4 6
CH5 7
14 V
DD
13 SCK
12 SO
11 SI
10 CS
9 V
SS
8 V
REF
MCP6S28
PDIP, SOIC
V
OUT
1
CH0 2
CH1 3
CH2 4
CH3 5
CH4 6
CH5 7
CH6 8
16 V
DD
15 SCK
14 SO
13 SI
12 CS
11 V
SS
10 V
REF
9 CH7
POR
V
SS
V
REF
2003-2012 Microchip Technology Inc.
DS21117B-page 1
MCP6S21/2/6/8
1.0
ELECTRICAL
CHARACTERISTICS
PIN FUNCTION TABLE
Name
Function
Absolute Maximum Ratings †
V
DD
- V
SS
.........................................................................7.0V
All inputs and outputs ....................... V
SS
- 0.3V to V
DD
+0.3V
Difference Input voltage ........................................ |V
DD
- V
SS
|
Output Short Circuit Current...................................continuous
Current at Input Pin
2
mA
Current at Output and Supply Pins
30
mA
Storage temperature .....................................-65°C to +150°C
Junction temperature .................................................. +150°C
ESD protection on all pins (HBM;MM)
2
kV; 200V
† Notice:
Stresses above those listed under "Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect
device reliability.
V
OUT
CH0-CH7
V
SS
V
DD
SCK
SI
SO
CS
V
REF
Analog Output
Analog Inputs
Negative Power Supply
Positive Power Supply
SPI Clock Input
SPI Serial Data Input
SPI Serial Data Output
SPI Chip Select
External Reference Pin
DC CHARACTERISTICS
Electrical Specifications:
Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.5V to +5.5V, V
SS
= GND, V
REF
= V
SS
, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, R
L
= 10 kto V
DD
/2, SI and SCK are tied low and CS is tied high.
Parameters
Amplifier Input
Input Offset Voltage
Input Offset Voltage Drift
Power Supply Rejection Ratio
Input Bias Current
Input Bias Current over
Temperature
Input Impedance
Input Voltage Range
Amplifier Gain
Nominal Gains
DC Gain Error
DC Gain Drift
Internal Resistance
Internal Resistance over
Temperature
Amplifier Output
DC Output Non-linearity G = +1
G
+2
Maximum Output Voltage Swing
V
ONL
V
ONL
V
OH
, V
OL
—
—
V
SS
+20
V
SS
+60
Short-Circuit Current
I
O(SC)
—
±0.003
±0.001
—
—
±30
—
—
V
DD
-100
V
DD
-60
—
mA
% of FSR V
OUT
= 0.3V to V
DD
0.3V,
V
DD
= 5.0V
% of FSR V
OUT
= 0.3V to V
DD
0.3V,
V
DD
= 5.0V
mV
G
+2; 0.5V output overdrive
G
+2; 0.5V output overdrive,
V
REF
= V
DD
/2
G = +1
G
+2
G = +1
G
+2
—
g
E
g
E
G/T
A
G/T
A
R
LAD
R
LAD
/T
A
—
-0.1
-1.0
—
—
3.4
—
1 to 32
—
—
±0.0002
±0.0004
4.9
+0.028
—
+0.1
+1.0
—
—
6.4
—
V/V
%
%
%/°C
%/°C
k
%/°C
+1, +2, +4, +5, +8, +10, +16 or +32
V
OUT
0.3V to V
DD
0.3V
V
OUT
0.3V to V
DD
0.3V
T
A
= -40 to +85°C
T
A
= -40 to +85°C
(Note 1)
(Note 1)
T
A
= -40 to +85°C
V
OS
V
OS
/T
A
PSRR
I
B
I
B
Z
IN
V
IVR
-275
—
70
—
—
—
V
SS
0.3
—
±4
85
±1
—
10
13
||15
—
+275
—
—
—
250
—
V
DD
+0.3
µV
µV/°C
dB
pA
pA
||pF
V
G = +1, V
DD
= 4.0V
T
A
= -40 to +85°C
G = +1
(Note 1)
CHx = V
DD
/2
T
A
= -40 to +85°C,
CHx = V
DD
/2
Sym
Min
Typ
Max
Units
Conditions
Note 1:
R
LAD
(R
F
+ R
G
in Figure 4-1) connects V
REF
, V
OUT
and the inverting input of the internal amplifier. The MCP6S22 has
V
REF
tied internally to V
SS
, so V
SS
is coupled to the internal amplifier and the PSRR spec describes PSRR+ only. We
recommend the MCP6S22’s V
SS
pin be tied directly to ground to avoid noise problems.
2:
I
Q
includes current in R
LAD
(typically 60 µA at V
OUT
= 0.3V). Both I
Q
and I
Q_SHDN
exclude digital switching currents.
3:
The output goes Hi-Z and the registers reset to their defaults; see Section 5.4, “Power-On Reset”.
DS21117B-page 2
2003-2012 Microchip Technology Inc.
MCP6S21/2/6/8
DC CHARACTERISTICS (CONTINUED)
Electrical Specifications:
Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.5V to +5.5V, V
SS
= GND, V
REF
= V
SS
, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, R
L
= 10 kto V
DD
/2, SI and SCK are tied low and CS is tied high.
Parameters
Power Supply
Supply Voltage
Quiescent Current
Quiescent Current, Shutdown
mode
Power-On Reset
POR Trip Voltage
POR Trip Voltage Drift
V
POR
V
POR
/T
1.2
—
1.7
-3.0
2.2
—
V
mV/°C
(Note 3)
T
A
= -40°C to+85°C
V
DD
I
Q
I
Q_SHDN
2.5
0.5
—
—
1.0
0.5
5.5
1.35
1.0
V
mA
µA
I
O
= 0
(Note 2)
I
O
= 0
(Note 2)
Sym
Min
Typ
Max
Units
Conditions
Note 1:
R
LAD
(R
F
+ R
G
in Figure 4-1) connects V
REF
, V
OUT
and the inverting input of the internal amplifier. The MCP6S22 has
V
REF
tied internally to V
SS
, so V
SS
is coupled to the internal amplifier and the PSRR spec describes PSRR+ only. We
recommend the MCP6S22’s V
SS
pin be tied directly to ground to avoid noise problems.
2:
I
Q
includes current in R
LAD
(typically 60 µA at V
OUT
= 0.3V). Both I
Q
and I
Q_SHDN
exclude digital switching currents.
3:
The output goes Hi-Z and the registers reset to their defaults; see Section 5.4, “Power-On Reset”.
AC CHARACTERISTICS
Electrical Specifications:
Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.5V to +5.5V, V
SS
= GND, V
REF
= V
SS
, G = +1 V/V,
Input = CH0 =(0.3V)/G, CH1 to CH7=0.3V, R
L
= 10 kto V
DD
/2, C
L
= 60 pF, SI and SCK are tied low, and CS is tied high.
Parameters
Frequency Response
-3 dB Bandwidth
Gain Peaking
Total Harmonic Distortion plus Noise
f = 1 kHz, G = +1 V/V
f = 1 kHz, G = +4 V/V
f = 1 kHz, G = +16 V/V
f = 20 kHz, G = +1 V/V
f = 20 kHz, G = +4 V/V
f = 20 kHz, G = +16 V/V
Step Response
Slew Rate
SR
—
—
—
Noise
Input Noise Voltage
Input Noise Voltage Density
Input Noise Current Density
E
ni
e
ni
i
ni
—
—
—
—
3.2
26
10
4
—
—
—
—
µV
P-P
f = 0.1 Hz to 10 kHz
(Note 2)
f = 0.1 Hz to 200 kHz
(Note 2)
nV/Hz f = 10 kHz
(Note 2)
fA/Hz f = 10 kHz
4.0
11
22
—
—
—
V/µs
V/µs
V/µs
G = 1, 2
G = 4, 5, 8, 10
G = 16, 32
THD+N
THD+N
THD+N
THD+N
THD+N
THD+N
—
—
—
—
—
—
0.0015
0.0058
0.023
0.0035
0.0093
0.036
—
—
—
—
—
—
%
%
%
%
%
%
V
OUT
= 1.5V ± 1.0V
PK
, V
DD
= 5.0V,
BW = 22 kHz
V
OUT
= 1.5V ± 1.0V
PK
, V
DD
= 5.0V,
BW = 22 kHz
V
OUT
= 1.5V ± 1.0V
PK
, V
DD
= 5.0V,
BW = 22 kHz
V
OUT
= 1.5V ± 1.0V
PK
, V
DD
= 5.0V,
BW = 80 kHz
V
OUT
= 1.5V ± 1.0V
PK
, V
DD
= 5.0V,
BW = 80 kHz
V
OUT
= 1.5V ± 1.0V
PK
, V
DD
= 5.0V,
BW = 80 kHz
BW
GPK
—
—
2 to 12
0
—
—
MHz
dB
All gains; V
OUT
< 100 mV
P-P
(Note 1)
All gains; V
OUT
< 100 mV
P-P
Sym
Min
Typ
Max
Units
Conditions
Note 1:
See Table 4-1 for a list of typical numbers.
2:
E
ni
and e
ni
include ladder resistance noise. See Figure 2-33 for e
ni
vs. G data.
2003-2012 Microchip Technology Inc.
DS21117B-page 3
MCP6S21/2/6/8
DIGITAL CHARACTERISTICS
Electrical Specifications:
Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.5V to +5.5V, V
SS
= GND, V
REF
= V
SS
, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, R
L
= 10 kto V
DD
/2, C
L
= 60 pF, SI and SCK are tied low, and CS is tied high.
Parameters
SPI Inputs (CS, SI, SCK)
Logic Threshold, Low
Input Leakage Current
Logic Threshold, High
Amplifier Output Leakage Current
Logic Threshold, Low
Logic Threshold, High
SPI Timing
Pin Capacitance
Input Rise/Fall Times (CS, SI, SCK)
Output Rise/Fall Times (SO)
CS high time
SCK edge to CS fall setup time
CS fall to first SCK edge setup time
SCK Frequency
SCK high time
SCK low time
SCK last edge to CS rise setup time
CS rise to SCK edge setup time
SI set-up time
SI hold time
SCK to SO valid propagation delay
CS rise to SO forced to zero
Channel and Gain Select Timing
Channel Select Time
t
CH
—
1.5
—
µs
CHx = 0.6V, CHy =0.3V, G = 1,
CHx to CHy select
CS
= 0.7V
DD
to
V
OUT
90% point
CHx = 0.3V, G = 5 to G = 1 select,
CS
= 0.7V
DD
to
V
OUT
90% point
CS = 0.7V
DD
to V
OUT
90% point
C
PIN
t
RFI
t
RFO
t
CSH
t
CS0
t
CSSC
f
SCK
t
HI
t
LO
t
SCCS
t
CS1
t
SU
t
HD
t
DO
t
SOZ
—
—
—
40
10
40
—
40
40
30
100
40
10
—
—
10
—
5
—
—
—
—
—
—
—
—
—
—
—
—
—
2
—
—
—
—
10
—
—
—
—
—
—
80
80
pF
µs
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
MCP6S26 and MCP6S28
MCP6S26 and MCP6S28
SCK edge when CS is high
V
DD
= 5V
(Note 2)
SCK edge when CS is high
All digital I/O pins
Note 1
MCP6S26 and MCP6S28
V
IL
I
IL
V
IH
—
V
OL
V
OH
0
-1.0
0.7V
DD
-1.0
V
SS
V
DD
-0.5
—
—
—
—
—
—
0.3V
DD
+1.0
V
DD
+1.0
V
SS
+0.4
V
DD
V
µA
V
µA
V
V
In Shutdown mode
I
OL
= 2.1 mA, V
DD
= 5V
I
OH
= -400 µA
Sym
Min
Typ
Max
Units
Conditions
SPI Output (SO, for MCP6S26 and MCP6S28)
Gain Select Time
Shutdown Mode Timing
Out of Shutdown mode (CS goes
high) to Amplifier Output Turn-on
Time
Into Shutdown mode (CS goes high)
to Amplifier Output High-Z Turn-off
Time
POR Timing
Power-On Reset power-up time
Power-On Reset power-down time
t
G
—
1
—
µs
t
ON
—
3.5
10
µs
t
OFF
—
1.5
—
µs
CS = 0.7V
DD
to V
OUT
90% point
t
RPU
t
RPD
—
—
30
10
—
—
µs
µs
V
DD
= V
POR
- 0.1V to V
POR
+ 0.1V,
50% V
DD
to 90% V
OUT
point
V
DD
= V
POR
+ 0.1V to V
POR
- 0.1V,
50% V
DD
to 90% V
OUT
point
Note 1:
Not tested in production. Set by design and characterization.
2:
When using the device in the daisy chain configuration, maximum clock frequency is determined by a combination of
propagation delay time (t
DO
80 ns), data input setup time (t
SU
40 ns), SCK high time (t
HI
40 ns), and SCK rise and
fall times of 5 ns. Maximum f
SCK
is, therefore,
5.8 MHz.
DS21117B-page 4
2003-2012 Microchip Technology Inc.
MCP6S21/2/6/8
TEMPERATURE CHARACTERISTICS
Electrical Specifications:
Unless otherwise indicated, V
DD
= +2.5V to +5.5V, V
SS
= GND.
Parameters
Temperature Ranges
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistances
Thermal Resistance, 8L-PDIP
Thermal Resistance, 8L-SOIC
Thermal Resistance, 8L-MSOP
Thermal Resistance, 14L-PDIP
Thermal Resistance, 14L-SOIC
Thermal Resistance, 14L-TSSOP
Thermal Resistance, 16L-PDIP
Thermal Resistance, 16L-SOIC
JA
JA
JA
JA
JA
JA
JA
JA
—
—
—
—
—
—
—
—
85
163
206
70
120
100
70
90
—
—
—
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
T
A
T
A
T
A
-40
-40
-65
—
—
—
+85
+125
+150
°C
°C
°C
(Note 1)
Sym
Min
Typ
Max
Units
Conditions
Note 1:
The MCP6S21/2/6/8 family of PGAs operates over this extended temperature range, but with reduced
performance. Operation in this range must not cause T
J
to exceed the Maximum Junction Temperature
(150°C).
CS
t
CH
CS
t
G
V
OUT
0.6V
0.3V
V
OUT
1.5V
0.3V
FIGURE 1-1:
Diagram.
Channel Select Timing
FIGURE 1-3:
Diagram.
Gain Select Timing
CS
t
ON
t
OFF
V
DD
V
POR
- 0.1V
V
POR
+ 0.1V
t
RPU
V
POR
- 0.1V
t
RPD
V
OUT
Hi-Z
0.3V
Hi-Z
V
OUT
Hi-Z
0.3V
1.0 mA (typ)
500 nA (typ)
Hi-Z
I
SS
500 nA (typ)
1.0 mA (typ)
I
SS
FIGURE 1-2:
PGA Shutdown timing
diagram (must enter correct commands before
CS goes high).
FIGURE 1-4:
POR power-up and power-
down timing diagram.
2003-2012 Microchip Technology Inc.
DS21117B-page 5
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