MC74LVX573
Octal D-Type Latch
with 3-State Outputs
With 5 V−Tolerant Inputs
The MC74LVX573 is an advanced high speed CMOS octal latch
with 3−state outputs. The inputs tolerate voltages up to 7.0 V, allowing
the interface of 5.0 V systems to 3.0 V systems.
This 8−bit D−type latch is controlled by a latch enable input and an
output enable input. When the output enable input is high, the eight
outputs are in a high impedance state.
Features
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•
•
•
•
•
•
•
•
High Speed: t
PD
= 6.4 ns (Typ) at V
CC
= 3.3 V
Low Power Dissipation: I
CC
= 4
mA
(Max) at T
A
= 25°C
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Low Noise: V
OLP
= 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: Human Body Model > 2000 V;
Machine Model > 200 V
•
These Devices are Pb−Free and are RoHS Compliant
SOIC−20
DW SUFFIX
CASE 751D
TSSOP−20
DT SUFFIX
CASE 948E
PIN ASSIGNMENT
V
CC
O0
20
19
O1
18
O2
17
O3
16
O4
15
O5
14
O6
13
O7
12
LE
11
1
OE
2
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
10
GND
20−Lead
(Top View)
MARKING DIAGRAMS
20
LVX573
AWLYYWWG
1
SOIC−20
LVX573
A
WL, L
Y
WW, W
G or
G
1
TSSOP−20
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
20
LVX
573
ALYWG
G
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 5
Publication Order Number:
MC74LVX573/D
MC74LVX573
OE
LE
1
11
nLE
Q
D
18
Q
D
17
Q
D
16
Q
D
nLE
Q
D
14
Q
D
nLE
Q
D
12
Q
D
O7
13
O6
O5
15
O4
O3
O2
O1
OE
L
L
L
L
L
H
H
H
H
H
19
O0
Table 1. PIN NAMES
Pins
OE
LE
D0−D7
O0−O7
Function
Output Enable Input
Latch Enable Input
Data Inputs
3−State Latch Outputs
2
D0
3
D1
nLE
INPUTS
LE
H
H
L
L
L
L
H
H
L
L
Dn
H
L
h
l
X
X
H
L
h
l
OUTPUTS
On
H
L
H
L
NC
Z
Z
Z
Z
Z
OPERATING MODE
Transparent (Latch
Disabled); Read Latch
Latched (Latch Enabled)
Read Latch
Hold; Read Latch
Hold; Disabled Outputs
Transparent (Latch
Disabled); Disabled Outputs
Latched (Latch Enabled);
Disabled Outputs
4
D2
nLE
5
D3
nLE
6
D4
7
D5
nLE
8
D6
H = High Voltage Level; h = High Voltage Level One Setup Time
Prior to the Latch Enable High−to−Low Transition; L = Low
Voltage Level; l = Low Voltage Level One Setup Time Prior to the
Latch Enable High−to−Low Transition; NC = No Change, State
Prior to the Latch Enable High−to−Low Transition; X = High or
Low Voltage Level or Transitions are Acceptable; Z = High
Impedance State; For I
CC
Reasons DO NOT FLOAT Inputs.
9
D7
nLE
Figure 1. Logic Diagram
MAXIMUM RATINGS
Symbol
V
CC
V
in
V
out
I
IK
I
OK
I
out
I
CC
P
D
T
stg
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation
Storage Temperature
Parameter
Value
–0.5 to +7.0
–0.5 to +7.0
–0.5 to V
CC
+0.5
−20
±20
±25
±75
180
–65 to +150
Unit
V
V
V
mA
mA
mA
mA
mW
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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2
MC74LVX573
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
V
out
T
A
Dt/DV
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Operating Temperature, All Package Types
Input Rise and Fall Time
Parameter
Min
2.0
0
0
−40
0
Max
3.6
5.5
V
CC
+85
100
Unit
V
V
V
°C
ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
V
CC
V
2.0
3.0
3.6
2.0
3.0
3.6
I
OH
= −50
mA
I
OH
= −50
mA
I
OH
= −4 mA
I
OL
= 50
mA
I
OL
= 50
mA
I
OL
= 4 mA
V
in
= 5.5 V or GND
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
V
in
= V
CC
or GND
2.0
3.0
3.0
2.0
3.0
3.0
3.6
3.6
3.6
1.9
2.9
2.58
2.0
3.0
0.0
0.0
0.1
0.1
0.36
±0.1
±0.2
5
4.0
T
A
= 25°C
Min
1.5
2.0
2.4
0.5
0.8
0.8
1.9
2.9
2.48
0.1
0.1
0.44
±1.0
±2.5
40.0
Typ
Max
T
A
= −40 to 85°C
Min
1.5
2.0
2.4
0.5
0.8
0.8
Max
Unit
V
Symbol
V
IH
Parameter
High−Level Input Voltage
Test Conditions
V
IL
Low−Level Input Voltage
V
V
OH
High−Level Output Voltage
(V
in
= V
IH
or V
IL
)
Low−Level Output Voltage
(V
in
= V
IH
or V
IL
)
Input Leakage Current
Maximum 3−State Leakage Current
Quiescent Supply Current
V
V
OL
V
I
in
I
OZ
I
CC
mA
mA
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
AC ELECTRICAL CHARACTERISTICS
(Input t
r
= t
f
= 3.0ns)
T
A
= 25°C
Symbol
t
PLH
,
t
PHL
Parameter
Propagation Delay
LE to O
Test Conditions
V
CC
= 2.7 V
V
CC
= 3.3
±
0.3 V
t
PLH
,
t
PHL
Propagation Delay
D to O
V
CC
= 2.7 V
V
CC
= 3.3
±
0.3 V
t
PZL
,
t
PZH
Output Enable Time
OE to O
V
CC
= 2.7 V
R
L
= 1 kW
V
CC
= 3.3
±
0.3 V
R
L
= 1 kW
t
PLZ
,
t
PHZ
Output Disable Time
OE to O
V
CC
= 2.7 V
R
L
= 1 kW
V
CC
= 3.3
±
0.3 V
R
L
= 1 kW
t
OSHL
t
OSLH
Output−to−Output Skew
(Note 1)
V
CC
= 2.7 V
V
CC
= 3.3
±
0.3 V
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 50 pF
C
L
= 50 pF
C
L
= 50 pF
C
L
= 50 pF
Min
Typ
8.2
10.7
6.4
8.9
7.6
10.1
5.9
8.4
7.8
10.3
6.1
8.6
12.1
10.1
Max
15.6
19.1
10.1
13.6
14.5
18.0
9.3
12.8
15.0
18.5
9.7
13.2
19.1
13.6
1.5
1.5
T
A
= −40 to 85°C
Min
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
18.5
22.0
12.0
15.5
17.5
21.0
11.0
14.5
18.5
22.0
12.0
15.5
22.0
15.5
1.5
1.5
ns
ns
ns
ns
Unit
ns
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t
OSHL
) or LOW−to−HIGH (t
OSLH
); parameter
guaranteed by design.
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MC74LVX573
CAPACITIVE CHARACTERISTICS
T
A
= 25°C
Symbol
C
in
C
out
C
PD
Input Capacitance
Maximum 3−State Output Capacitance
Power Dissipation Capacitance (Note 2)
Parameter
Min
Typ
4
6
29
Max
10
T
A
= −40 to 85°C
Min
Max
10
Unit
pF
pF
pF
2. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
/ 8 (per latch). C
PD
is used to determine the
no−load dynamic power consumption; P
D
= C
PD
V
CC2
f
in
+ I
CC
V
CC
.
NOISE CHARACTERISTICS
(Input t
r
= t
f
= 3.0 ns, C
L
= 50 pF, V
CC
= 3.3 V, Measured in SOIC Package)
T
A
= 25°C
Symbol
V
OLP
V
OLV
V
IHD
V
ILD
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
Characteristic
Typ
0.5
−0.5
Max
0.8
−0.8
2.0
0.8
Unit
V
V
V
V
TIMING REQUIREMENTS
(Input t
r
= t
f
= 3.0 ns)
T
A
= 25°C
Symbol
t
w(h)
t
su
t
h
Parameter
Minimum Pulse Width, LE
Minimum Setup Time, D to LE
Minimum Hold Time, D to LE
Test Conditions
V
CC
= 2.7 V
V
CC
= 3.3
±
0.3 V
V
CC
= 2.7 V
V
CC
= 3.3
±
0.3 V
V
CC
= 2.7 V
V
CC
= 3.3
±
0.3 V
Typ
Limit
6.5
5.0
5.0
3.5
1.5
1.5
T
A
= −40 to 85°C
Limit
7.5
5.0
5.0
3.5
1.5
1.5
Unit
ns
ns
ns
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MC74LVX573
SWITCHING WAVEFORMS
V
CC
D
t
PLH
O
50% V
CC
O
50% V
CC
50%
GND
t
PHL
t
PLH
t
PHL
LE
50%
GND
t
w
V
CC
Figure 2.
Figure 3.
OE
V
CC
50%
GND
t
PZL
O
50% V
CC
t
PZH
O
50% V
CC
t
PHZ
VOL −0.3 V
HIGH
IMPEDANCE
t
PLZ
HIGH
IMPEDANCE
VOL +0.3 V
LE
D
50%
t
su
GND
t
h
V
CC
50%
GND
VALID
V
CC
Figure 4.
Figure 5.
TEST CIRCUITS
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 kW
CONNECT TO V
CC
WHEN
TESTING t
PLZ
AND t
PZL
.
CONNECT TO GND WHEN
TESTING t
PHZ
AND t
PZH
.
C
L
*
C
L
*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 6. Propagation Delay Test Circuit
Figure 7. 3−State Test Circuit
ORDERING INFORMATION
Device
MC74LVX573DWR2G
MC74LVX573DTG
MC74LVX573DTR2G
Package
SOIC−20
(Pb−Free)
TSSOP−20
(Pb−Free)
TSSOP−20
(Pb−Free)
Shipping
†
1000 / Tape & Reel
75 Units / Rail
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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