Intel
®
Xeon
®
E-2100 Processor
Family
Datasheet, Volume 1 of 2
August 2018
Revision 001
Document Number: 338012-001
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2
Intel
®
Xeon
®
E-2100 Processor Family
Datasheet, Volume 1 of 2, August 2018
Contents
1
Introduction
.............................................................................................................. 9
1.1
Supported Technologies ..................................................................................... 12
1.2
Power Management Support ............................................................................... 12
1.2.1 Processor Core Power Management........................................................... 12
1.2.2 System Power Management ..................................................................... 12
1.2.3 Memory Controller Power Management...................................................... 13
1.2.4 Processor Graphics Power Management ..................................................... 13
1.3
Thermal Management Support ............................................................................ 13
1.4
Package Support ............................................................................................... 14
1.5
Ballout Information............................................................................................ 14
1.6
Processor Testability .......................................................................................... 14
1.7
Terminology ..................................................................................................... 14
1.8
Related Documents ........................................................................................... 16
Interfaces................................................................................................................
18
2.1
System Memory Interface .................................................................................. 18
2.1.1 System Memory Technology Supported ..................................................... 18
2.1.2 System Memory Timing Support............................................................... 19
2.1.3 System Memory Organization Modes......................................................... 20
2.1.4 System Memory Frequency...................................................................... 21
2.1.5 Technology Enhancements of Intel
®
Fast Memory Access (Intel
®
FMA).......... 21
2.1.6 Data Scrambling .................................................................................... 22
2.1.7 DDR I/O Interleaving .............................................................................. 22
2.1.8 Data Swapping ...................................................................................... 23
2.1.9 DRAM Clock Generation........................................................................... 23
2.1.10 DRAM Reference Voltage Generation ......................................................... 23
2.2
PCI Express* Graphics Interface (PEG)................................................................. 23
2.2.1 PCI Express Support ............................................................................... 23
2.2.2 PCI Express Architecture ......................................................................... 25
2.2.3 PCI Express Configuration Mechanism ....................................................... 26
2.2.4 PCI Express Equalization Methodology....................................................... 26
2.3
Direct Media Interface (DMI)............................................................................... 27
2.3.1 DMI Lane Reversal and Polarity Inversion .................................................. 27
2.3.2 DMI Error Flow....................................................................................... 28
2.3.3 DMI Link Down ...................................................................................... 28
2.4
Processor Graphics ............................................................................................ 29
2.4.1 Operating Systems Support ..................................................................... 29
2.4.2 API Support (Windows*) ......................................................................... 29
2.4.3 Media Support (Intel
®
QuickSync and Clear Video Technology HD) ............... 30
2.4.4 Switchable/Hybrid Graphics ..................................................................... 32
2.4.5 Gen 9 LP Video Analytics ......................................................................... 33
2.4.6 Gen 9 LP (9th Generation Low Power) Block Diagram .................................. 34
2.4.7 GT2 Graphic Frequency ........................................................................... 34
2.5
Display Interfaces ............................................................................................. 35
2.5.1 DDI Configuration .................................................................................. 35
2.5.2 eDP* Bifurcation .................................................................................... 36
2.5.3 Display Technologies .............................................................................. 36
2.5.4 DisplayPort* .......................................................................................... 39
2.5.5 High-Definition Multimedia Interface (HDMI*) ............................................ 39
2.5.6 Digital Video Interface (DVI) .................................................................... 40
2.5.7 embedded DisplayPort* (eDP*) ................................................................ 40
2
Intel
®
Xeon
®
E-2100 Processor Family
Datasheet, Volume 1 of 2, August 2018
3
2.6
3
2.5.8 Integrated Audio ....................................................................................40
2.5.9 Multiple Display Configurations (Dual Channel DDR) ....................................41
2.5.10 Multiple Display Configurations (Single Channel DDR) ..................................42
2.5.11 High-Bandwidth Digital Content Protection (HDCP) ......................................42
2.5.12 Display Link Data Rate Support ................................................................43
2.5.13 Display Bit Per Pixel (BPP) Support............................................................44
2.5.14 Display Resolution per Link Width .............................................................44
Platform Environmental Control Interface (PECI) ....................................................44
2.6.1 PECI Bus Architecture..............................................................................44
Technologies............................................................................................................47
3.1
Intel
®
Virtualization Technology (Intel
®
VT) ..........................................................47
3.1.1 Intel
®
Virtualization Technology (Intel
®
VT) for IA-32, Intel
®
64 and Intel
®
Architecture (Intel
®
VT-X)........................................................................47
3.1.2 Intel
®
Virtualization Technology (Intel
®
VT) for Directed I/O (Intel
®
VT-d).....50
3.2
Security Technologies.........................................................................................52
3.2.1 Intel
®
Trusted Execution Technology (Intel
®
TXT) .......................................52
3.2.2 Intel
®
Advanced Encryption Standard New Instructions (Intel
®
AES-NI) .........53
3.2.3 PCLMULQDQ (Perform Carry-Less Multiplication Quad word) Instruction .........54
3.2.4 Intel
®
Secure Key ...................................................................................54
3.2.5 Execute Disable Bit .................................................................................54
3.2.6 Intel
®
Boot Guard Technology ..................................................................54
3.2.7 Intel
®
Supervisor Mode Execution Protection (SMEP) ...................................55
3.2.8 Intel
®
Supervisor Mode Access Protection (SMAP) .......................................55
3.2.9 Intel
®
Memory Protection Extensions (Intel
®
MPX)......................................55
3.2.10 Intel
®
Software Guard Extensions (Intel
®
SGX) ..........................................56
3.2.11 Intel
®
Virtualization Technology (Intel
®
VT) for Directed I/O (Intel
®
VT-d).....56
3.3
Power and Performance Technologies ...................................................................57
3.3.1 Intel
®
Hyper-Threading Technology (Intel
®
HT Technology) .........................57
3.3.2 Intel
®
Turbo Boost Technology 2.0............................................................57
3.3.3 Intel
®
Advanced Vector Extensions 2 (Intel
®
AVX2) ....................................58
3.3.4 Intel
®
64 Architecture x2APIC ..................................................................58
3.3.5 Power Aware Interrupt Routing (PAIR).......................................................59
3.3.6 Intel
®
Transactional Synchronization Extensions (Intel
®
TSX-NI) ..................59
3.4
Debug Technologies ...........................................................................................60
3.4.1 Intel
®
Processor Trace ............................................................................60
Power Management
.................................................................................................61
4.1
Advanced Configuration and Power Interface (ACPI) States Supported ......................63
4.2
Processor IA Core Power Management ..................................................................65
4.2.1 OS/HW Controlled P-States ......................................................................65
4.2.2 Low-Power Idle States.............................................................................66
4.2.3 Requesting Low-Power Idle States ............................................................67
4.2.4 Processor IA Core C-State Rules ...............................................................67
4.2.5 Package C-States ...................................................................................69
4.2.6 Package C-States and Display Resolutions..................................................72
4.3
Integrated Memory Controller (IMC) Power Management.........................................73
4.3.1 Disabling Unused System Memory Outputs.................................................73
4.3.2 DRAM Power Management and Initialization ...............................................73
4.3.3 DDR Electrical Power Gating (EPG) ............................................................75
4.3.4 Power Training .......................................................................................76
4.4
PCI Express Power Management ..........................................................................76
4.5
Direct Media Interface (DMI) Power Management ...................................................77
4.6
Processor Graphics Power Management ................................................................77
4.6.1 Memory Power Savings Technologies.........................................................77
4.6.2 Display Power Savings Technologies ..........................................................77
4
4
Intel
®
Xeon
®
E-2100 Processor Family
Datasheet, Volume 1 of 2, August 2018
4.7
5
4.6.3 Processor Graphics Core Power Savings Technologies .................................. 79
Voltage Optimization.......................................................................................... 79
Thermal Management
.............................................................................................. 80
5.1
Processor Thermal Management .......................................................................... 80
5.1.1 Thermal Considerations........................................................................... 80
5.1.2 Intel
®
Turbo Boost Technology 2.0 Power Monitoring .................................. 81
5.1.3 Intel Turbo Boost Technology 2.0 Power Control ......................................... 81
5.1.4 Thermal Management Features ................................................................ 83
5.2
All-Processor Line Thermal and Power Specifications .............................................. 89
5.3
Intel
®
Xeon
®
E-2100 Processor Family Thermal and Power Specifications ................. 90
5.3.1 Thermal Metrology ................................................................................. 92
5.3.2 Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 2.0 ................ 92
Signal Description
................................................................................................... 94
6.1
System Memory Interface .................................................................................. 94
6.2
PCI Express Graphics (PEG) Signals ..................................................................... 96
6.3
Direct Media Interface (DMI) Signals.................................................................... 96
6.4
Reset and Miscellaneous Signals .......................................................................... 97
6.5
embedded DisplayPort* (eDP*) Signals ................................................................ 98
6.6
Display Interface Signals .................................................................................... 98
6.7
Processor Clocking Signals.................................................................................. 98
6.8
Testability Signals ............................................................................................. 99
6.9
Error and Thermal Protection Signals ................................................................... 99
6.10 Power Sequencing Signals ................................................................................ 100
6.11 Processor Power Rails ...................................................................................... 101
6.12 Ground, Reserved and Non-Critical to Function (NCTF) Signals .............................. 101
6.13 Processor Internal Pull-Up/Pull-Down Terminations .............................................. 102
Electrical Specifications
......................................................................................... 103
7.1
Processor Power Rails ...................................................................................... 103
7.1.1 Power and Ground Pins ......................................................................... 103
7.1.2 V
CC
Voltage Identification (VID) ............................................................. 103
7.2
DC Specifications ............................................................................................ 104
7.2.1 Processor Power Rails DC Specifications .................................................. 104
7.2.2 Processor Interfaces DC Specifications .................................................... 109
Package Mechanical Specifications
........................................................................ 114
8.1
Package Mechanical Attributes .......................................................................... 114
8.2
Package Storage Specifications ......................................................................... 114
6
7
8
Figures
1-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
3-1
Processor Line Platform........................................................................................... 11
Intel
®
Flex Memory Technology Operations ............................................................... 20
Interleave (IL) and Non-Interleave (NIL) Modes Mapping............................................. 23
PCI Express Related Register Structures in the Processor............................................. 26
Example for DMI Lane Reversal Connection ............................................................... 28
Video Analytics Common Use Cases .......................................................................... 33
Gen 9 LP Block Diagram .......................................................................................... 34
Processor Display Architecture (With 3 DDI Ports as an Example) ................................. 38
DisplayPort Overview.............................................................................................. 39
HDMI Overview...................................................................................................... 40
Example for PECI Host-Clients Connection ................................................................. 45
Example for PECI EC Connection .............................................................................. 46
Device to Domain Mapping Structures ....................................................................... 51
Intel
®
Xeon
®
E-2100 Processor Family
Datasheet, Volume 1 of 2, August 2018
5
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