74LVT16543A
Rev. 3 — 1 October 2018
3.3 V 16-bit registered transceiver; 3-state
Product data sheet
1. General description
The 74LVT16543A is a high-performance BiCMOS product designed for V
CC
operation at 3.3 V.
The device can be used as two 8-bit transceivers or one 16-bit transceiver.
The 74LVT16543A contains two sets of eight D-type latches, with separate control pins for each
set. Using data flow from A to B as an example, when the A-to-B enable (nEAB) input and the
A-to-B latch enable (nLEAB) input are LOW, the A-to-B path is transparent.
A subsequent LOW-to-HIGH transition of the nLEAB signal puts the A data into the latches where it
is stored and the B outputs no longer change with the A inputs. With nEAB and nOEAB both LOW,
the 3-State B output buffers are active and display the data present at the outputs of the A latches.
Control of data flow from B to A is similar, but using the nEBA, nLEBA, and nOEBA inputs.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
2. Features and benefits
•
•
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•
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16-bit universal bus interface
3-state buffers
Input and output interface capability to systems at 5 V supply
TTL input and output switching levels
Output capability: +64 mA/-32 mA
Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs
Live insertion/extraction permitted
Power-up 3-state
Power-up reset
No bus current loading when output is tied to 5 V bus
Latch-up protection:
•
JESD78B Class II exceeds 500 mA
ESD protection:
•
HBM: JESD22-A114F exceeds 2000 V
•
MM: JESD22-A115-A exceeds 200 V
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74LVT16543ADL
74LVT16543ADGG
-40 °C to +85 °C
-40 °C to +85 °C
SSOP56
TSSOP56
Description
plastic shrink small outline package; 56 leads;
body width 7.5 mm
Version
SOT371-1
plastic thin shrink small outline package; 56 leads; SOT364-1
body width 6.1 mm
Nexperia
74LVT16543A
3.3 V 16-bit registered transceiver; 3-state
5.2. Pin description
Table 2. Pin description
Symbol
1A0, 1A1, 1A2, 1A3, 1A4, 1A5, 1A6, 1A7
2A0, 2A1, 2A2, 2A3, 2A4, 2A5, 2A6, 2A7
1B0, 1B1, 1B2, 1B3, 1B4, 1B5, 1B6, 1B7
2B0, 2B1, 2B2, 2B3, 2B4, 2B5, 2B6, 2B7
1OEAB, 1OEBA, 2OEAB, 2OEBA
1EAB, 1EBA, 2EAB, 2EBA
1LEAB, 1LEBA, 2LEAB, 2LEBA
GND
V
CC
Pin
5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24
52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33
1, 56, 28, 29
3, 54, 26, 31
2, 55, 27, 30
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
Description
data inputs/outputs
data inputs/outputs
data inputs/outputs
data inputs/outputs
A to B / B to A output enable inputs
(active LOW)
A to B / B to A enable inputs
(active LOW)
A to B / B to A latch enable inputs
(active LOW)
ground (0 V)
supply voltage
6. Functional description
Table 3. Function selection
[1]
Inputs
nOEAB or nOEBA nEAB or nEBA
H
X
L
L
L
L
L
L
L
[1]
Outputs
nLEAB or nLEBA nAn or nBn
X
X
L
L
↑
↑
L
L
H
X
X
h
l
h
l
H
L
X
nBn or nAn
Z
Z
Z
Z
H
L
H
L
NC
Status
Disabled
Disabled
Disabled + Latch
Disabled + Latch
Latch + Display
Latch + Display
Transparent
Transparent
Hold
X
H
↑
↑
L
L
L
L
L
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH transition of nLEAB, nLEBA, nEAB and nEBA;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH transition of nLEAB, nLEBA, nEAB and nEBA;
X = don’t care;
↑ = LOW-to-HIGH transition of nLEAB, nLEBA, nEAB or nEBA;
NC = no change;
Z = high-impedance OFF-state.
74LVT16543A
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 3 — 1 October 2018
5 / 16
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