CBTL06141
Gen1 display 2 : 1 multiplexer
Rev. 2 — 15 July 2010
Product data sheet
1. General description
The CBTL06141 is a six-channel (‘hex’) multiplexer for DisplayPort and PCI Express
applications at Generation 1 (‘Gen1’) speeds. It provides four differential channels
capable of 1 : 2 switching or 2 : 1 multiplexing (bidirectional and AC-coupled) PCI Express
or DisplayPort signals, using high-bandwidth pass-gate technology. Additionally, it
provides for switching/multiplexing of the Hot Plug Detect signal as well as the AUX or
DDC (Direct Display Control) signals, for a total of six channels on the display side. The
AUX and DDC channels provide a four-position multiplexer such that an additional level of
multiplexing can be accomplished when AUX and DDC I/Os are on separate pins of the
display source device.
The CBTL06141 is designed for Gen1 speeds, at 2.5 Gbit/s for PCI Express or 2.7 Gbit/s
for DisplayPort, and for inputs voltages of up to 3.3 V typical. It consumes very low current
in operational mode (less than 1 mA typical) and provides for a shutdown function (less
than 10
μA)
to support battery-powered applications.
A typical application of CBTL06141 is on motherboards where one of two GPU display
sources needs to be selected to connect to a display sink device or connector. A controller
chip selects which path to use by setting a select signal HIGH or LOW. Due to the
non-directional nature of the signal paths (which use high-bandwidth passgate
technology), the CBTL06141 can also be used in the reverse topology, e.g., to connect
one display source device to one of two display sink devices or connectors.
Optionally, the hex MUX device can be used in conjunction with an HDMI/DVI level shifter
device (PTN3300A, PTN3300B or PTN3301) to allow for DisplayPort as well as HDMI/DVI
connectivity.
2. Features and benefits
1 : 2 switching or 2 : 1 multiplexing of DisplayPort (v1.1 - 2.7 Gbit/s) or PCI Express
(v1.1 - 2.5 Gbit/s) signals
4 high-speed differential channels with 2 : 1 muxing/switching for DisplayPort or
PCI Express signals
1 channel with 4 : 1 muxing/switching for AUX differential signals or DDC
single-ended clock and data signals
1 channel with 2 : 1 muxing/switching for single-ended HPD signals
High-bandwidth analog pass-gate technology
Very low intra-pair differential skew (< 5 ps)
Very low inter-pair skew (< 180 ps)
Switch/multiplexer position select CMOS input
Shutdown mode CMOS input
NXP Semiconductors
CBTL06141
Gen1 display 2 : 1 multiplexer
Shutdown mode minimizes power consumption while switching all channels off
DDC and AUX ports tolerant to being pulled to +5 V via 2.2 kΩ resistor
Supports HDMI/DVI incorrect dongle connection
Single 3.3 V power supply
Very low operation current of 0.2 mA typical
Very low shutdown current of < 10
μA
ESD 8 kV HBM, 1 kV CDM
ESD 2 kV HBM, 500 V CDM for control pins
Available in 5 mm
×
5 mm, 0.5 mm ball pitch TFBGA48 package
3. Applications
Motherboard applications requiring DisplayPort and PCI Express
switching/multiplexing
Docking stations
Notebook computers
Chip sets requiring flexible allocation of PCI Express or DisplayPort I/O pins to board
connectors
4. Ordering information
Table 1.
Ordering information
Solder process
Pb-free (SnAgCu
solder compound)
Package
Name
CBTL06141EE/G
TFBGA48
Description
Version
plastic thin fine-pitch ball grid array package; 48 balls; SOT918-1
body 5
×
5
×
0.8 mm
[1]
Type number
[1]
Total height including solder balls after printed circuit board mounting = 1.15 mm.
CBTL06141
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 15 July 2010
2 of 18
NXP Semiconductors
CBTL06141
Gen1 display 2 : 1 multiplexer
5. Functional diagram
VDD
CBTL06141
4
DIN1_n+
DIN1_n−
DIN2_n+
DIN2_n−
0
4
4
DOUT_n+
DOUT_n−
1
DAUX1+
DAUX1−
DAUX2+
DAUX2−
DDC_CLK1
DDC_DAT1
DDC_CLK2
DDC_DAT2
00
10
AUX+ or SCL
AUX− or SDA
AUX+
AUX−
01
11
HPD_1
0
HPDIN
HPD_2
1
GPU_SEL
DDC_AUX_SEL
TST0
XSD
GND
002aad554
Fig 1.
Functional diagram
CBTL06141
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 15 July 2010
3 of 18
NXP Semiconductors
CBTL06141
Gen1 display 2 : 1 multiplexer
6. Pinning information
6.1 Pinning
ball A1
index area
CBTL06141EE/G
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
002aad360
Transparent top view
Fig 2.
Pin configuration for TFBGA48
1
A
B
C
D
E
F
G
H
J
AUX−
HPDIN
DOUT_1−
DOUT_2−
DOUT_3−
GPU_SEL
DOUT_0−
2
VDD
DOUT_0+
DDC_AUX
_SEL
DOUT_1+
DOUT_2+
DOUT_3+
TST0
AUX+
HPD_1
3
4
DIN1_0−
5
DIN1_1−
DIN1_1+
6
DIN1_2−
DIN1_2+
7
8
DIN1_3+
9
DIN1_3−
DIN2_0−
GND
DIN1_0+
XSD
DIN2_0+
GND
DIN2_1+
DIN2_2+
DIN2_3+
GND
DIN2_1−
DIN2_2−
DIN2_3−
HPD_2
GND
VDD
DDC_CLK2
DDC_DAT2
DAUX2+
DAUX2−
GND
DDC_CLK1
DDC_DAT1
DAUX1+
DAUX1−
002aad361
Transparent top view
Fig 3.
Ball mapping
CBTL06141
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 15 July 2010
4 of 18
NXP Semiconductors
CBTL06141
Gen1 display 2 : 1 multiplexer
6.2 Pin description
Table 2.
Symbol
GPU_SEL
Pin description
Ball
A1
Type
3.3 V low-voltage CMOS
single-ended input
Description
Selects between two multiplexer/switch paths. When HIGH, path 2
left-side is connected to its corresponding right-side I/O. When
LOW, path 1 left-side is connected to its corresponding right-side
I/O.
Selects between DDC and AUX paths. When HIGH, the CLK and
DAT I/Os are connected to their respective DDCOUT terminals.
When LOW, the AUX+ and AUX− I/Os are connected to their
respective DDCOUT terminals.
Shutdown pin. Should be driven HIGH or connected to VDD for
normal operation. When LOW, all paths are switched off
(non-conducting) and supply current consumption is minimized.
Test pin for NXP use only. Should be tied to ground in normal
operation.
Four high-speed differential pairs for DisplayPort or PCI Express
signals, path 1, left-side.
DDC_AUX_SEL
C2
3.3 V low-voltage CMOS
single-ended input
XSD
B7
3.3 V low-voltage CMOS
single-ended input
3.3 V low-voltage CMOS
single-ended input
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
TST0
DIN1_0+
DIN1_0−
DIN1_1+
DIN1_1−
DIN1_2+
DIN1_2−
DIN1_3+
DIN1_3−
DIN2_0+
DIN2_0−
DIN2_1+
DIN2_1−
DIN2_2+
DIN2_2−
DIN2_3+
DIN2_3−
DOUT_0+
DOUT_0−
DOUT_1+
DOUT_1−
DOUT_2+
DOUT_2−
DOUT_3+
DOUT_3−
DAUX1+
DAUX1−
DAUX2+
DAUX2−
G2
B4
A4
B5
A5
B6
A6
A8
A9
B8
B9
D8
D9
E8
E9
F8
F9
B2
B1
D2
D1
E2
E1
F2
F1
H9
J9
H6
J6
Four high-speed differential pairs for DisplayPort or PCI Express
signals, path 2, left-side.
Four high-speed differential pairs for DisplayPort or PCI Express
signals, right-side.
High-speed differential pair for AUX signals, path 1, left-side.
High-speed differential pair for AUX signals, path 2, left-side.
CBTL06141
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 15 July 2010
5 of 18
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