................................................................................................................. -0.6V to +6.5V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature under bias............................................................................................................... -40°C to +85°C
ESD protection on all pins.......................................................................................................................................... 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Industrial (I):
Min.
.7 V
CC
-0.3
-0.3
—
—
V
CC
-0.5
T
AMB
= -40°C to +85°C
Max.
V
CC
+1
0.3V
CC
0.2V
CC
0.4
0.2
—
±1
±1
—
7
Units
V
V
V
V
V
V
A
A
pF
V
CC
2.5V
V
CC
< 2.5V
I
OL
= 2.1 mA
I
OL
= 1.0 mA, V
CC
< 2.5V
I
OH
= -400
A
CS = V
CC
, V
IN
= V
SS TO
V
CC
CS = V
CC
, V
OUT
= V
SS TO
V
CC
T
AMB
= 25°C, CLK = 1.0 MHz
V
CC
= 5.0V
(Note
1)
V
CC
= 5.5V; F
CLK
= 10.0 MHz
SO = Open
V
CC
= 5.5V
V
BAT
= 1.8V @ 25°C
(Note
2)
1.5V typical at T
AMB
= 25°C
From V
TRIP
(max) to V
TRIP
(min)
From V
TRIP
(min) to V
TRIP
(max)
—
V
CC
= 3V
V
CC
= 1.8V to 5.5V
Test Conditions
DC CHARACTERISTICS
Param.
No.
D001
D002
D003
D004
D005
D006
D007
D008
D009
Sym.
V
IH1
V
IL1
V
IL2
V
OL
V
OL
V
OH
I
LI
I
LO
C
INT
Characteristic
High-level input
voltage
Low-level input
voltage
Low-level output
voltage
High-level output
voltage
Input leakage current
Output leakage
current
Internal Capacitance
(all inputs and
outputs)
D010
D011
D012
D013
D014
D015
D016
D017
I
CC
Read Operating Current
I
DD
write Write Current
I
BAT
V
TRIP
VCCFT
VCCRT
V
BAT
I
CCS
V
BAT
Current
V
BAT
Change Over
V
CC
Fall Time
V
CC
Rise Time
V
BAT
Voltage Range
Standby Current
—
—
—
1.3
300
0
1.3
—
3
5
700
1.7
mA
mA
nA
V
s
s
5.5
1
V
A
Note 1:
This parameter is periodically sampled and not 100% tested.
2:
With oscillator running.
2011-2012 Microchip Technology Inc.
Preliminary
DS22280B-page 3
MCP795WXX/MCP795BXX
TABLE 1-2:
Param.
No.
1
AC CHARACTERISTICS
Industrial (I):
Min.
—
—
—
50
100
150
50
100
150
50
10
20
30
20
40
50
—
—
50
100
150
50
100
150
50
50
—
—
—
0
—
—
—
—
1,000,000
T
AMB
= -40°C to +85°C V
CC
= 1.8V to 5.5V
Max.
10
5
3
—
—
—
—
—
—
—
—
—
—
—
—
—
100
100
—
—
—
—
—
—
—
—
50
100
160
—
40
80
160
5
—
Units
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Test Conditions
4.5V
Vcc
5.5V
2.5V
Vcc
4.5V
1.8V
Vcc
2.5V
4.5V
Vcc
5.5V
2.5V
Vcc
4.5V
1.8V
Vcc
2.5V
4.5V
Vcc
5.5V
2.5V
Vcc
4.5V
1.8V
Vcc
2.5V
—
4.5V
Vcc
5.5V
2.5V
Vcc
4.5V
1.8V
Vcc
2.5V
4.5V
Vcc
5.5V
2.5V
Vcc
4.5V
1.8V
Vcc
2.5V
(Note
1)
(Note
1)
4.5V
Vcc
5.5V
2.5V
Vcc
4.5V
1.8V
Vcc
2.5V
4.5V
Vcc
5.5V
2.5V
Vcc
4.5V
1.8V
Vcc
2.5V
—
—
4.5V
Vcc
5.5V
2.5V
Vcc
4.5V
1.8V
Vcc
2.5V
(Note
1)
4.5V
Vcc
5.5V
(Note
1)
2.5V
Vcc
4.5V
(Note
1)
1.8V
Vcc
2.5V
(Note
1)
(Note
3)
AC CHARACTERISTICS
Sym.
F
CLK
Characteristic
Clock Frequency
2
T
CSS
CS Setup Time
3
T
CSH
CS Hold Time
4
5
T
CSD
Tsu
CS Disable Time
Data Setup Time
6
T
HD
Data Hold Time
7
8
9
T
R
T
F
T
HI
CLK Rise Time
CLK Fall Time
Clock High Time
10
T
LO
Clock Low Time
11
12
13
T
CLD
T
CLE
T
V
Clock Delay Time
Clock Enable Time
Output Valid from Clock
Low
Output Hold Time
Output Disable Time
14
15
T
HO
T
DIS
16
17
T
WC
—
Internal Write Cycle Time
Endurance
E/W
(Note
2)
Cycles
Note 1:
This parameter is periodically sampled and not 100% tested.
2:
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site:
www.microchip.com.
3:
T
WC
begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle
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