MCP3911
3.3V Two-Channel Analog Front End
Features
• Two Synchronous Sampling 16/24-bit Resolution
Delta-Sigma A/D Converters
• 94.5 dB SINAD, -106.5 dBc Total Harmonic
Distortion (THD) (up to 35
th
harmonic), 111 dB
SFDR for Each Channel
• 2.7V-3.6V AV
DD
, DV
DD
• Programmable Data Rate Up to 125 ksps:
- 4 MHz Maximum Sampling Frequency
• Oversampling Ratio Up to 4096
• Ultra Low-Power Shutdown Mode with <2 µA
• -122 dB Crosstalk Between the Two Channels
• Low-Drift 1.2V Internal Voltage Reference:
7 ppm/°C
• Differential Voltage Reference Input Pins
• High-Gain Programmable Gain Amplifier (PGA)
on Each Channel (up to 32V/V)
• Phase Delay Compensation with 1 µs Time
Resolution
• Separate Modulator Output Pins for Each
Channel
• Separate Data Ready Pin for Easy
Synchronization
• Individual 24-Bit Digital Offset and Gain Error
Correction for Each Channel
• High-Speed 20 MHz SPI Interface with Mode 0,0
and 1,1 Compatibility
• Continuous Read/Write Modes for Minimum
Communication
• Low-Power Consumption (8.9 mW at 3.3V,
5.6 mW at 3.3V in Low-Power mode, typical)
• Available in Small 20-Lead QFN and SSOP
Packages, Pin-to-Pin Compatible with MCP3901
• Extended Temperature Range: -40°C to +125°C
Description
The MCP3911 is a 2.7V to 3.6V dual channel Analog
Front End (AFE) containing two synchronous sampling
Delta-Sigma Analog-to-Digital Converters (ADC), two
PGAs, phase delay compensation block, low-drift
internal voltage reference, modulator output block,
Digital Offset and Gain Error Calibration registers and
high-speed 20 MHz SPI compatible serial interface.
The MCP3911 ADCs are fully configurable with
features, such as: 16/24-bit resolution, Oversampling
Ratio (OSR) from 32 to 4096, gain from 1x to 32x,
independent shutdown and Reset, dithering and auto-
zeroing. The communication is largely simplified with the
one-byte long commands, including various continuous
Read/Write modes that can be accessed by the Direct
Memory Access (DMA) of an MCU with a separate Data
Ready pin that can be directly connected to an Interrupt
Request (IRQ) input of an MCU.
The MCP3911 is capable of interfacing a large variety
of voltage and current sensors, including shunts,
current transformers, Rogowski coils and Hall effect
sensors.
Package Type
20-Lead
SSOP
RESET
DV
DD
AV
DD
CH0+
CH0-
CH1-
CH1+
A
GND
REFIN+/OUT
REFIN-
DV
DD
1
2
3
4
5
6
7
8
9
10
RESET
20
19
18
17
16
15
14
13
12
11
SDI
SDO
SCK
CS
OSC2
OSC1/CLKI
DR
MDAT0
MDAT1
D
GND
20-Lead
4x4 QFN*
CH0+
1
CH0-
2
CH1-
3
CH1+
4
A
GND
5
AV
DD
20 19 18 17 16
Applications
•
•
•
•
•
Energy Metering and Power Measurement
Automotive
Portable Instrumentation
Medical and Power Monitoring
Audio/Voice Recognition
SDO
SDI
15
SCK
EP
21
14
CS
13
OSC2
12
OSC1/CLKI
11
DR
6
REFIN+/OUT
7
REFIN-
8
D
GND
9 10
MDAT1
MDAT0
*
Includes Exposed Thermal Pad (EP); see
Table 3-1.
2012-2020 Microchip Technology Inc.
DS20002286D-page 1
MCP3911
Functional Block Diagram
REFIN/OUT
AV
DD
Voltage
Reference
+
–
V
REF
VREFEXT
DV
DD
AMCLK
Clock
Generation
Xtal Oscillator
OSC1
MCLK
OSC2
REFIN-
DMCLK/DRCLK
V
REF
-
V
REF
+
ANALOG
DIGITAL
DMCLK
SINC
3
+
SINC
1
CH0+
CH0-
+
–
PGA
Modulator
MOD[3:0]
OSR[2:0]
PR[1:0]
OFFCAL_CH0 GAINCAL_CH0
[23:0]
[23:0]
+
X
DATA_CH0
[23:0]
DR
SDO
Digital SPI
Interface
RESET
SDI
SCK
CS
CH1+
CH1-
+
–
PGA
Phase
PHASE[11:0]
Shifter
OFFCAL_CH1 GAINCAL_CH1
[23:0]
[23:0]
MOD[7:4]
+
SINC +
SINC
1
3
X
DATA_CH1
[23:0]
Modulator
DUAL
ADC
MODOUT[1:0]
MOD[7:0]
Modulator
Output Block
MDAT0
MDAT1
POR
AV
DD
Monitoring
POR
DV
DD
Monitoring
A
GND
D
GND
DS20002286D-page 2
2012-2020 Microchip Technology Inc.
MCP3911
1.0
ELECTRICAL
CHARACTERISTICS
† Notice:
Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at those or any other
conditions, above those indicated in the operational
listings of this specification, is not implied. Exposure to
maximum rating conditions for extended periods may
affect device reliability.
Absolute Maximum Ratings†
V
DD
..................................................................... -0.3V to 4.0V
Digital inputs and outputs w.r.t. A
GND
................. -0.3V to 4.0V
Analog input w.r.t. A
GND
..................................... ....-2V to +2V
V
REF
input w.r.t. A
GND
.............................. -0.6V to V
DD
+ 0.6V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD on the analog inputs (HBM,MM) ................. 4.0 kV, 300V
ESD on all other pins (HBM,MM) ........................ 4.0 kV, 300V
1.1
Electrical Specifications
ANALOG SPECIFICATIONS TARGET
TABLE 1-1:
Electrical Specifications:
Unless otherwise indicated, all parameters apply at AV
DD
= DV
DD
= 2.7V to 3.6V; MCLK = 4 MHz;
PRE[1:0] =
00;
OSR = 256; GAIN =
1;
VREFEXT =
0;
CLKEXT =
1;
AZ_FREQ =
0;
DITHER[1:0] =
11;
BOOST[1:0] =
10;
V
CM
= 0V; T
A
= -40°C to +125°C; V
IN
= 1.2 V
PP
= 424 mV
RMS
at 50/60 Hz on both channels.
Characteristic
ADC Performance
Resolution (No Missing
Codes)
Sampling Frequency
Output Data Rate
Analog Input Absolute
Voltage on CH0+, CH0-,
CH1+, CH1- Pins
Analog Input
Leakage Current
Differential Input
Voltage Range
Offset Error
Offset Error Drift
Gain Error
Note 1:
GE
f
S
(DMCLK)
f
D
(DRCLK)
CH0+/-
24
—
—
-1
—
1
4
—
—
4
125
+1
bits
MHz
ksps
V
OSR = 256 or greater
For maximum condition,
BOOST[1:0] =
11
For maximum condition,
BOOST[1:0] =
11,
OSR = 32
All analog input channels,
measured to A
GND
RESET[1:0] =
11,
MCLK running continuously
V
REF
= 1.2V,
proportional to V
REF
Note 4
Note 4
Sym
Min
Typ
Max
Units
Conditions
I
IN
—
±1
—
0.2
0.5
—
—
+600/GAIN
+2
—
+6
nA
mV
mV
µV/°C
%
(CHn+ – CHn-) -600/GAIN
V
OS
-2
—
-6
2:
3:
4:
5:
6:
This specification implies that the ADC output is valid over this entire differential range and that there is no
distortion or instability across this input range. Dynamic performance specified at -0.5 dB below the maximum
signal range, V
IN
= 1.2 V
PP
= 424 mV
RMS
, V
REF
= 1.2V at 50/60 Hz. See
Section 4.0, Terminologies and
Formulas
for definition. This parameter is established by characterization and is not 100% tested. See
performance graphs for other than default settings provided here.
For these operating currents, the following Configuration bit settings apply: SHUTDOWN[1:0] =
00,
RESET[1:0] =
00,
VREFEXT =
0,
CLKEXT =
0.
For these operating currents, the following Configuration bit settings apply: SHUTDOWN[1:0] =
11,
VREFEXT =
1,
CLKEXT =
1.
Applies to all gains. Offset and gain errors depend on PGA gain setting; see
Section 2.0, Typical Performance
Curves
for typical performance.
Outside of this range, the ADC accuracy is not specified. An extended input range of ±2V can be applied
continuously to the part with no damage.
For proper operation and optimizing ADC accuracy, AMCLK should be limited to the maximum frequency defined
in
Table 5-2
as a function of the BOOST and PGA settings chosen. MCLK can take larger values as long as the
prescaler settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE in the defined range in
Table 5-2.
2012-2020 Microchip Technology Inc.
DS20002286D-page 3
MCP3911
TABLE 1-1:
ANALOG SPECIFICATIONS TARGET (CONTINUED)
Electrical Specifications:
Unless otherwise indicated, all parameters apply at AV
DD
= DV
DD
= 2.7V to 3.6V; MCLK = 4 MHz;
PRE[1:0] =
00;
OSR = 256; GAIN =
1;
VREFEXT =
0;
CLKEXT =
1;
AZ_FREQ =
0;
DITHER[1:0] =
11;
BOOST[1:0] =
10;
V
CM
= 0V; T
A
= -40°C to +125°C; V
IN
= 1.2 V
PP
= 424 mV
RMS
at 50/60 Hz on both channels.
Characteristic
Gain Error Drift
Integral Nonlinearity
Differential Input
Impedance
INL
Z
IN
Sym
Min
—
—
232
142
72
38
36
33
Signal-to-Noise and
Distortion Ratio
(Note
1)
Total Harmonic Distortion
(Note
1)
Signal-to-Noise Ratio
(Note
1)
Spurious-Free Dynamic
Range
(Note
1)
Crosstalk (50, 60 Hz)
AC Power Supply Rejection
DC Power
Supply Rejection
DC Common-Mode
Rejection
Note 1:
SINAD
THD
SNR
SFDR
CTALK
AC PSRR
DC PSRR
DC CMRR
92
—
92
—
—
—
—
—
Typ
1
5
—
—
—
—
—
—
94.5
-106.5
95
111
-122
-73
-73
-105
Max
—
—
—
—
—
—
—
—
—
-103
—
—
—
—
—
—
Units
ppm/°C
ppm
k
k
k
k
k
k
dB
dBc
dB
dBFS
dB
dB
dB
dB
AV
DD
= DV
DD
= 3.3V + 0.6V
PP,
50/60 Hz, 100/120 Hz
AV
DD
= DV
DD
= 2.7V to 3.6V
V
CM
from -1V to +1V
Includes the first 35 harmonics
G = 1, proportional to 1/AMCLK
G = 2, proportional to 1/AMCLK
G = 4, proportional to 1/AMCLK
G = 8, proportional to 1/AMCLK
G = 16, proportional to 1/AMCLK
G = 32, proportional to 1/AMCLK
Conditions
2:
3:
4:
5:
6:
This specification implies that the ADC output is valid over this entire differential range and that there is no
distortion or instability across this input range. Dynamic performance specified at -0.5 dB below the maximum
signal range, V
IN
= 1.2 V
PP
= 424 mV
RMS
, V
REF
= 1.2V at 50/60 Hz. See
Section 4.0, Terminologies and
Formulas
for definition. This parameter is established by characterization and is not 100% tested. See
performance graphs for other than default settings provided here.
For these operating currents, the following Configuration bit settings apply: SHUTDOWN[1:0] =
00,
RESET[1:0] =
00,
VREFEXT =
0,
CLKEXT =
0.
For these operating currents, the following Configuration bit settings apply: SHUTDOWN[1:0] =
11,
VREFEXT =
1,
CLKEXT =
1.
Applies to all gains. Offset and gain errors depend on PGA gain setting; see
Section 2.0, Typical Performance
Curves
for typical performance.
Outside of this range, the ADC accuracy is not specified. An extended input range of ±2V can be applied
continuously to the part with no damage.
For proper operation and optimizing ADC accuracy, AMCLK should be limited to the maximum frequency defined
in
Table 5-2
as a function of the BOOST and PGA settings chosen. MCLK can take larger values as long as the
prescaler settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE in the defined range in
Table 5-2.
DS20002286D-page 4
2012-2020 Microchip Technology Inc.
MCP3911
TABLE 1-1:
ANALOG SPECIFICATIONS TARGET (CONTINUED)
Electrical Specifications:
Unless otherwise indicated, all parameters apply at AV
DD
= DV
DD
= 2.7V to 3.6V; MCLK = 4 MHz;
PRE[1:0] =
00;
OSR = 256; GAIN =
1;
VREFEXT =
0;
CLKEXT =
1;
AZ_FREQ =
0;
DITHER[1:0] =
11;
BOOST[1:0] =
10;
V
CM
= 0V; T
A
= -40°C to +125°C; V
IN
= 1.2 V
PP
= 424 mV
RMS
at 50/60 Hz on both channels.
Characteristic
Internal Voltage Reference
Tolerance
Temperature Coefficient
Output Impedance
Internal Voltage Reference
Operating Current
Voltage Reference Input
Input Capacitance
Differential Input Voltage
Range (V
REF
+ – V
REF
-)
Absolute Voltage on
REFIN+ Pin
Absolute Voltage on
REFIN- Pin
Master Clock Input
Master Clock Input
Frequency Range
Crystal Oscillator
Operating Frequency
Range
Analog Master Clock
Power Supply
Operating Voltage, Analog
Operating Voltage, Digital
Operating Current,
Analog
(Note
2)
AV
DD
DV
DD
I
DD,A
2.7
2.7
—
—
—
—
Note 1:
—
—
1.5
1.8
2.5
4.4
3.6
3.6
2.3
2.8
3.5
6.25
V
V
mA
mA
mA
mA
BOOST[1:0] =
00
BOOST[1:0] =
01
BOOST[1:0] =
10
BOOST[1:0] =
11
f
MCLK
f
XTAL
—
1
—
—
20
20
MHz
MHz
CLKEXT =
1
(Note
6)
CLKEXT =
0
(Note
6)
V
REF
V
REF
+
V
REF
-
—
1.1
V
REF
- + 1.1
-0.1
—
—
—
—
10
1.3
V
REF
- + 1.3
+0.1
pF
V
V
V
VREFEXT =
1
VREFEXT =
1
REFIN- should be connected to
A
GND
when VREFEXT =
0
V
REF
TCV
REF
ZOUTV
REF
AI
DD
V
REF
1.176
—
—
—
1.2
7
2
25
1.224
—
—
—
V
VREFEXT =
0,
T
A
= +25°C only
ppm/°C T
A
= -40°C to +125°C,
VREFEXT =
0
k
µA
VREFEXT =
0
VREFEXT =
0,
SHUTDOWN[1:0] =
11
Sym
Min
Typ
Max
Units
Conditions
AMCLK
—
—
16
MHz
Note 6
2:
3:
4:
5:
6:
This specification implies that the ADC output is valid over this entire differential range and that there is no
distortion or instability across this input range. Dynamic performance specified at -0.5 dB below the maximum
signal range, V
IN
= 1.2 V
PP
= 424 mV
RMS
, V
REF
= 1.2V at 50/60 Hz. See
Section 4.0, Terminologies and
Formulas
for definition. This parameter is established by characterization and is not 100% tested. See
performance graphs for other than default settings provided here.
For these operating currents, the following Configuration bit settings apply: SHUTDOWN[1:0] =
00,
RESET[1:0] =
00,
VREFEXT =
0,
CLKEXT =
0.
For these operating currents, the following Configuration bit settings apply: SHUTDOWN[1:0] =
11,
VREFEXT =
1,
CLKEXT =
1.
Applies to all gains. Offset and gain errors depend on PGA gain setting; see
Section 2.0, Typical Performance
Curves
for typical performance.
Outside of this range, the ADC accuracy is not specified. An extended input range of ±2V can be applied
continuously to the part with no damage.
For proper operation and optimizing ADC accuracy, AMCLK should be limited to the maximum frequency defined
in
Table 5-2
as a function of the BOOST and PGA settings chosen. MCLK can take larger values as long as the
prescaler settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE in the defined range in
Table 5-2.
2012-2020 Microchip Technology Inc.
DS20002286D-page 5
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