74ALVCH16601
Rev. 3 — 13 August 2018
18-bit universal bus transceiver; 3-state
Product data sheet
1. General description
The 74ALVCH16601 is an 18-bit universal transceiver featuring non-inverting 3-state bus
compatible outputs in both send and receive directions. Data flow in each direction is controlled by
output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA)
inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH.
When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is
LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When
OEAB is LOW, the outputs are active. When OEAB is HIGH, the outputs are in the high-impedance
state. The clocks can be controlled with the clock-enable inputs (CEBA and CEAB).
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA.
To ensure the high impedance state during power up or power down, OEBA and OEAB should
be tied to V
CC
through a pullup resistor; the minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
2. Features and benefits
•
•
•
•
•
•
•
•
CMOS low power consumption
MultiByte flow-through standard pin-out architecture
Low inductance multiple V
CC
and GND pins for minimum noise and ground bounce
Direct interface with TTL levels
Bus hold on data inputs
Output drive capability 50 Ω transmission lines at 85 °C
Current drive ±24 mA at 3.0 V
Complies with JEDEC standards:
•
JESD8-5 (2.3 V to 2.7 V)
•
JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
•
HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V
•
CDM JESD22-C101E exceeds 1000 V
•
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74ALVCH16601DGG −40 °C to +85 °C
Name
TSSOP56
Description
plastic thin shrink small outline package;
56 leads; body width 6.1 mm
Version
SOT364-1
Nexperia
74ALVCH16601
18-bit universal bus transceiver; 3-state
5.2. Pin description
Table 2. Pin description
Symbol
A0, A1, A2, A3, A4, A5, A6, A7, A8,
A9, A10, A11, A12, A13, A14, A15, A16, A17
B0, B1, B2, B3, B4, B5, B6, B7, B8,
B9, B10, B11, B12, B13, B14, B15, B16, B17
OEAB, OEBA
LEAB, LEBA
CPBA, CPAB
CEBA, CEAB
GND
V
CC
Pin
3, 5, 6, 8, 9, 10, 12, 13, 14,
15, 16, 17, 19, 20, 21, 23, 24, 26
54, 52, 51, 49, 48, 47, 45, 44, 43,
42, 41, 40, 38, 37, 36, 34, 33, 31
1, 27
2, 28
30, 55
29, 56
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
Description
data inputs/outputs
data outputs/inputs
A to B / B to A output enable inputs
(active LOW)
A to B / B to A latch enable inputs
(active HIGH)
B to A / A to B clock inputs
(active HIGH)
B to A / A to B clock enable inputs
(active LOW)
ground (0 V)
supply voltage
6. Functional description
Table 3. Function selection
[1] [2]
Operating mode
Inputs
CEAB
Disabled
Transparent
Hold
Clock data & Display
Hold data & Display
X
X
X
H
L
L
L
L
[1]
[2]
Outputs
OEAB
H
L
L
L
L
L
L
L
LEAB
X
H
H
L
L
L
L
L
CPAB
X
X
X
X
↑
↑
H
L
An
X
H
L
X
h
l
X
X
Bn
Z
H
L
NC
H
L
NC
NC
A-to-B data flow is shown; B-to-A flow is similar but uses CEBA, OEBA, LEBA, and CPBA.
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the enable or clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the enable or clock transition;
X = don’t care;
NC = no change
↑ = LOW-to-HIGH enable or clock transition;
Z = high-impedance OFF-state.
74ALVCH16601
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 3 — 13 August 2018
5 / 15
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