MC74HCT541A
Octal 3-State Non-Inverting
Buffer/Line Driver/
Line Receiver With
LSTTL-Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT541A is identical in pinout to the LS541. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to high speed CMOS inputs.
The HCT541A is an octal non−inverting buffer/line driver/line
receiver designed to be used with 3−state memory address drivers,
clock drivers, and other bus−oriented systems. This device features
inputs and outputs on opposite sides of the package and two ANDed
active−low output enables.
Features
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SOIC−20
DW SUFFIX
CASE 751D
TSSOP−20
DT SUFFIX
CASE 948E
PIN ASSIGNMENT
V
CC
OE2 Y1
20 19 18
Y2
17
Y3
16
Y4
15
Y5
14
Y6
13
Y7
12
Y8
11
•
•
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
TTL/NMOS−Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1
mA
In Compliance With the JEDEC Standard No. 7 A Requirements
Chip Complexity: 134 FETs or 33.5 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•
These Devices are Pb−Free and are RoHS Compliant
LOGIC DIAGRAM
A1
A2
A3
A4
A5
A6
A7
A8
Output
Enables
OE1
OE2
2
3
4
5
6
7
8
9
1
19
PIN 20 = V
CC
PIN 10 = GND
1
18
17
16
15
14
13
12
11
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
1
2
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
10
GND
OE1 A1
MARKING DIAGRAMS
20
HCT541A
AWLYYWWG
1
SOIC−20
1
TSSOP−20
20
HCT
541A
ALYWG
G
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or
G
= Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Non-Inverting
Outputs
OE1
L
L
H
X
Inputs
OE2
L
L
X
H
A
L
H
X
X
L
H
Z
Z
Output Y
Data
Inputs
Z = High Impedance
X = Don’t Care
ORDERING INFORMATION
See detailed ordering and shipping information on page 4 of
this data sheet.
©
Semiconductor Components Industries, LLC, 2014
June, 2017 − Rev. 8
Publication Order Number:
MC74HCT541A/D
MC74HCT541A
MAXIMUM RATINGS
Symbol
V
CC
V
in
V
out
I
in
I
out
I
CC
P
D
T
stg
T
L
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
(SOIC Package)
SOIC Package†
Value
–0.5 to +7.0
–0.5 to V
CC
+ 0.5
–0.5 to V
CC
+ 0.5
±20
±35
±75
500
–65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
_C
_C
This device contains protection
circuitry to guard against damage due
to high static voltages or electric
fields. However, precautions must be
taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance
circuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be tied
to an appropriate logic voltage level
(e.g., either GND or V
CC
). Unused
outputs must be left open.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
, V
out
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage
(Referenced to GND)
Operating Temperature Range, All Package Types
Input Rise/Fall Time (Figure 1)
Min
4.5
0
–55
0
Max
5.5
V
CC
+125
500
Unit
V
V
_C
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC CHARACTERISTICS
(Voltages Referenced to GND)
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum High−Level Input Voltage
Maximum Low−Level Input Voltage
Minimum High−Level Output Voltage
Condition
V
out
= 0.1V or V
CC
− 0.1V
|I
out
|
≤
20mA
V
out
= 0.1V or V
CC
− 0.1V
|I
out
|
≤
20mA
V
in
= V
IH
or V
IL
|I
out
|
≤
20mA
V
in
= V
IH
or V
IL
V
OL
Maximum Low−Level Output Voltage
V
in
= V
IH
or V
IL
|I
out
|
≤
20mA
V
in
= V
IH
or V
IL
I
in
I
OZ
Maximum Input Leakage Current
Maximum 3−State Leakage Current
V
in
= V
CC
or GND
Output in High Impedance State
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
V
in
= V
CC
or GND
I
out
= 0mA
V
in
= 2.4V, Any One Input
V
in
= V
CC
or GND, Other Inputs
I
out
= 0mA
|I
out
|
≤
6.0mA
|I
out
|
≤
6.0mA
V
CC
V
4.5
5.5
4.5
5.5
4.5
5.5
4.5
4.5
5.5
4.5
5.5
5.5
Guaranteed Limit
−55 to 25°C
2.0
2.0
0.8
0.8
4.4
5.4
3.98
0.1
0.1
0.26
±0.1
±0.5
≤85°C
2.0
2.0
0.8
0.8
4.4
5.4
3.84
0.1
0.1
0.33
±1.0
±5.0
≤125°C
2.0
2.0
0.8
0.8
4.4
5.4
3.70
0.1
0.1
0.40
±1.0
±10.0
mA
mA
V
Unit
V
V
V
I
CC
DI
CC
Maximum Quiescent Supply Current
(per Package)
Additional Quiescent Supply Current
5.5
4
≥
−55°C
40
160
mA
25 to 125°C
2.4
mA
5.5
2.9
1. Total Supply Current = I
CC
+
ΣDI
CC
.
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2
MC74HCT541A
AC CHARACTERISTICS
(V
CC
= 5.0V, C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Guaranteed Limit
Symbol
t
PLH
,
t
PHL
t
PLZ
,
t
PHZ
t
PZL
,
t
PZH
t
TLH
,
t
THL
C
in
C
out
Parameter
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
Maximum Input Capacitance
Maximum 3−State Output Capacitance (Output in High Impedance State)
−55 to 25°C
23
30
30
12
10
15
≤85°C
28
34
34
15
10
15
≤125°C
32
38
38
18
10
15
Unit
ns
ns
ns
ns
pF
pF
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Per Buffer)*
55
pF
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC2
f + I
CC
V
CC
.
SWITCHING WAVEFORMS
t
r
90%
INPUT A
t
PLH
90%
OUTPUT Y
t
TLH
1.3V
10%
1.3V
10%
t
f
3.0V
OE1 or OE2
1.3V
t
PZL
GND
t
PHL
OUTPUT Y
1.3V
10%
t
PZH
t
THL
OUTPUT Y
1.3V
t
PHZ
90%
t
PLZ
1.3V
3.0V
GND
HIGH
IMPEDANCE
V
OL
V
OH
HIGH
IMPEDANCE
Figure 1.
Figure 2.
TEST CIRCUITS
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
C
L
*
DEVICE
UNDER
TEST
OUTPUT
TEST
POINT
1kW
CONNECT TO V
CC
WHEN
TESTING t
PLZ
AND t
PZL
.
CONNECT TO GND WHEN
TESTING t
PHZ
and t
PZH
.
C
L
*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 3.
Figure 4.
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3
MC74HCT541A
PIN DESCRIPTIONS
INPUTS
A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8,
9)
— Data input pins. Data on these pins appear in
non−inverted form on the corresponding Y outputs, when
the outputs are enabled.
CONTROLS
outputs are enabled and the device functions as a
non−inverting buffer. When a high voltage is applied to
either input, the outputs assume the high impedance state.
OUTPUTS
OE1, OE2 (PINS 1, 19)
— Output enables (active−low).
When a low voltage is applied to both of these pins, the
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14,
13, 12, 11)
— Device outputs. Depending upon the state of
the output enable pins, these outputs are either
non−inverting outputs or high−impedance outputs.
LOGIC DETAIL
To 7 Other Buf
fers
One of Eight
Buffers
INPUT A
V
CC
OUTPUT Y
OE1
OE2
ORDERING INFORMATION
Device
MC74HCT541ADWG
MC74HCT541ADWR2G
NLV74HCT541ADWR2G*
MC74HCT541ADTR2G
NLV74HCT541ADTR2G*
TSSOP−20
(Pb−Free)
SOIC−20
(Pb−Free)
Package
Shipping
†
38 Units / Rail
1000 / Tape & Reel
1000 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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4
MC74HCT541A
PACKAGE DIMENSIONS
TSSOP−20
DT SUFFIX
CASE 948E
ISSUE D
20X
K
REF
M
2X
L/2
20
11
J J1
B
L
PIN 1
IDENT
1
10
−U−
N
0.15 (0.006) T U
S
A
−V−
N
F
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
---
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0
_
8
_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
---
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0
_
8
_
C
D
0.100 (0.004)
−T−
SEATING
PLANE
G
H
DETAIL E
SOLDERING FOOTPRINT*
7.06
1
16X
0.36
16X
1.26
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
SECTION N−N
0.25 (0.010)
M
0.15 (0.006) T U
S
0.10 (0.004)
T U
S
V
S
K
K1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
−W−
0.65
PITCH
DIMENSIONS: MILLIMETERS
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