MCP2030
Three-Channel Analog Front-End Device
Device Features:
•
•
•
•
Three input pins for analog input signals
High input detection sensitivity (3 mV
PP
, typical)
High modulation depth sensitivity (as low as 8%)
Three output selections:
- Demodulated data
- Carrier clock
- RSSI
Input carrier frequency: 125 kHz, typical
Input data rate: 10 Kbps, maximum
8 internal Configuration registers
Bidirectional transponder communication
(LF talk back)
Programmable antenna tuning capacitance
(up to 63 pF, 1 pF/step)
Programmable output enable filter
Low standby current: 4
A
(with 3 channels
enabled), typical
Low operating current: 13
A
(with 3 channels
enabled), typical
Serial Peripheral Interface (SPI™) with external
devices
Supports Battery Back-Up mode and batteryless
operation with external circuits
Industrial and Extended Temperature Range:
-40°C to +85°C (industrial)
Description:
The MCP2030 is a stand-alone Analog Front-End
(AFE) device for Low-Frequency (LF) sensing and bidi-
rectional communication applications. The device has
eight internal Configuration registers which are
readable and programmable, except the read-only
STATUS register, by an external device.
The device has three low-frequency input channels.
Each input channel can be individually enabled or dis-
abled. The device can detect an input signal with ampli-
tude as low as ~1 mV
PP
and can demodulate an
amplitude-modulated input signal with as low as 8%
modulation depth. The device can also transmit data by
clamping and unclamping the input LC antenna
voltage.
The device can output demodulated data, carrier clock
or RSSI current depending on the register setting. The
demodulated data and carrier clock outputs are avail-
able on the LFDATA pin, while the RSSI output is avail-
able on the RSSI pin. The RSSI current output is
linearly proportional to the input signal strength.
The device has programmable internal tuning capaci-
tors for each input channel. The user can program
these capacitors up to 63 pF, 1 pF per step. These
internal tuning capacitors can be used effectively for
fine-tuning of the external LC resonant circuit.
The device is optimized for very low current consump-
tion and has various battery-saving low-power modes
(Sleep, Standby, Active). The device can also be oper-
ated in Battery Back-up and Batteryless modes using a
few external components.
This device is available in 14-pin PDIP, SOIC, and
TSSOP packages. This device is also used as the AFE
in the PIC16F639.
•
•
•
•
•
•
•
•
•
•
•
Typical Applications:
• Automotive industry applications:
- Passive Keyless Entry (PKE) transponder
- Remote door locks and gate openers
- Engine immobilizer
- LF initiator sensor for tire pressure monitoring
systems
• Security Industry applications:
- Long range access control transponder
- Parking lot entry transponder
- Hands-free apartment door access
- Asset control and management
Package Types:
MCP2030
PDIP, SOIC, TSSOP
V
SS
CS
SCLK/ALERT
RSSI
LFDATA/
CCLK/SDIO
V
DD
1
2
3
4
NC 5
6
7
14
13
V
SS
LCCOM
12 NC
LCX
11
10
9
8
LCY
LCZ
V
DD
2005-2013 Microchip Technology Inc.
DS21981B-page 1
MCP2030
NOTES:
DS21981B-page 2
2005-2013 Microchip Technology Inc.
MCP2030
1.0
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
(†)
Ambient temperature under bias...................-40°C to +125°C
Storage temperature .................................... -65°C to +150°C
Voltage on V
DD
with respect to V
SS
............... -0.3V to +6.5V
Voltage on all other pins with
respect to V
SS
...................................... -0.3V to (V
DD
+ 0.3V)
Maximum current out of V
SS
pin .................................300 mA
Maximum current into V
DD
pin ....................................250 mA
Maximum LC Input Voltage
(LCX, LCY, LCZ) loaded, with device........................ 10.0 V
PP
Maximum LC Input Voltage
(LCX, LCY, LCZ) unloaded, without device............. 700.0 V
PP
Maximum Input Current (rms) into device
per LC Channel.............................................................10 mA
Human Body ESD rating ....................................2000 (min.) V
Machine Model ESD rating ..................................200 (min.) V
† Notice:
Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect
device reliability.
DC Characteristics
Electrical Specifications:
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40C
T
A
+85C
LC Signal Input
Sinusoidal 300 mV
PP
Carrier Frequency
125 kHz
LCCOM connected to V
SS
Parameters
Supply Voltage
V
DD
Start Voltage to ensure internal
Power-on Reset signal
Modulation Transistor-on Resistance
Active Current (detecting signal)
1 LC Input Channel Receiving Signal
3 LC Input Channel Receiving Signals
Standby Current (wait to detect signal)
1 LC Input Channel Enabled
2 LC Input Channels Enabled
3 LC Input Channels Enabled
Sleep Current
Analog Input Leakage Current
LCX, LCY, LCZ
LCCOM
Digital Input Low Voltage
Digital Input High Voltage
Digital Input Leakage Current
(Note 1)
SDI
SCLK, CS
Digital Output Low Voltage
ALERT, LFDATA/SDIO
Digital Output High Voltage
ALERT, LFDATA/SDIO
Digital Input Pull-Up Resistor
CS, SCLK
*
†
1:
Sym.
V
DD
V
POR
R
M
I
ACT
—
—
I
STDBY
—
—
—
I
SLEEP
I
AIL
—
—
V
IL
V
IH
I
IL
—
—
V
OL
—
V
OH
V
DD
- 0.5
R
PU
50
—
200
—
350
V
k
—
V
SS
+0.4
V
—
—
V
SS
0.8 V
DD
—
—
—
—
—
2
3
4
0.2
5
6
7
1
1
1
0.3 V
DD
V
DD
1
1
10
13
—
18
Min.
2.0
—
—
Typ†
3.0
—
50
Max.
3.6
1.8
100
Units
V
V
V
DD
= 3.0V
CS = V
DD
Input = Continuous Wave (CW);
Amplitude = 300 mV
PP
.
All channels enabled.
CS = V
DD
; ALERT = V
DD
Conditions
A
A
A
A
A
A
A
A
V
V
CS = V
DD
; ALERT = V
DD
V
DD
= 3.6V, V
SS
V
IN
1V with respect to
ground. Internal tuning capacitors are switched
off, tested in Sleep mode.
SCLK, SDI, CS
SCLK, SDI, CS
V
DD
= 3.6V
V
SS
V
PIN
V
DD
V
PIN
V
DD
Analog Front-End section
I
OL
= 1.0 mA, V
DD
= 2.0V
I
OH
= -400
A, V
DD
= 2.0V
V
DD
= 3.6V
A
A
Note
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, +25C unless otherwise stated. These parameters are for design guidance only and are not tested.
Negative current is defined as current sourced by the pin.
2005-2013 Microchip Technology Inc.
DS21981B-page 3
MCP2030
AC Characteristics
Electrical Specifications:
Standard Operating Conditions (unless otherwise stated)
Supply Voltage
2.0V
V
DD
3.6V
Operating temperature
-40°C
T
A
+85°C
LCCOM connected to V
SS
LC Signal Input
Sinusoidal 300 mV
PP
Carrier Frequency
125 kHz
LCCOM connected to V
SS
Parameters
Input Sensitivity
Sym.
V
SENSE
1
3.0
6
mV
PP
Min.
Typ†
Max.
Units
Conditions
V
DD
= 3.0V
Output enable filter disabled
AGCSIG =
0;
MODMIN =
00
(33% modulation depth setting)
Input = Continuous Wave (CW)
Output = Logic level transition from
low-to-high at sensitivity level for CW input.
V
DD
= 3.0V, Force I
IN
= 5
A (worst case)
V
DD
= 2.0V, V
IN
= 8 V
DC
V
DD
= 3.0V
No sensitivity reduction selected
Max. reduction selected
Monotonic increment in attenuation value
from setting =
0000
to
1111
by design
V
DD
= 3.0V
See
Section 5.21 “Minimum Modulation
Depth Requirement for Input Signal”.
See Modulation Depth Definition in
Figure 5-5.
Coil de-Q’ing Voltage -
RF Limiter (R
FLM
) must be active
RF Limiter Turn-on Resistance
(LCX, LCY, LCZ)
Sensitivity Reduction
V
DE_Q
R
FLM
S
ADJ
3
—
—
300
5
700
V
—
—
0
-30
—
—
dB
dB
Minimum Modulation Depth
60% setting
33% setting
14% setting
8%
Carrier frequency
Input modulation frequency
V
IN_MOD
—
—
—
F
CARRIER
F
MOD
—
—
60
33
14
8
125
—
84
49
26
—
10
%
%
%
%
kHz
kHz
Input data rate with NRZ data format.
V
DD
= 3.0V
Minimum modulation depth setting = 33%
Input conditions:
Amplitude = 300 mV
PP
Modulation depth = 100%
V
DD
= 3.0V,
Config. Reg. 1, bits <6:1> Setting =
000000
63 pF ±30%
Config. Reg. 1, bits <6:1> Setting =
111111
63 steps, approx. 1 pF/step
Monotonic increment in capacitor value from
setting =
000000
to
111111
by design
V
DD
= 3.0V,
Config. Reg. 2, bits <6:1> Setting =
000000
63 pF ±30%
Config. Reg. 2, bits <6:1> Setting =
111111
63 steps, approx. 1 pF/step
Monotonic increment in capacitor value from
setting =
000000
to
111111
by design
V
DD
= 3.0V,
Config. Reg. 3, bits<6:1> Setting =
000000
63 pF ±30%
Config. Reg. 3, bits<6:1> Setting =
111111
63 steps, approx. 1 pF/step
Monotonic increment in capacitor value from
setting =
000000
to
111111
by design
LCX Tuning Capacitor
C
TUNX
—
44
0
59
—
82
pF
pF
LCY Tuning Capacitor
C
TUNY
—
44
0
59
—
82
pF
pF
LCZ Tuning Capacitor
C
TUNZ
—
44
0
59
—
82
pF
pF
Q of Internal Tuning Capacitors
Demodulator Charge Time
(delay time of demodulated output to rise)
Q_C
T
DR
50 *
—
—
50
—
—
s
V
DD
= 3.0V
Minimum modulation depth setting = 33%
Input conditions:
Amplitude = 300 mV
PP
Modulation depth = 100%
Note
*
†
1:
2:
Parameter is characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Required output enable filter high time must account for input path analog delays (= T
OEH
- T
DR
+ T
DF
).
Required output enable filter low time must account for input path analog delays (= T
OEL
+ T
DR
- T
DF
).
DS21981B-page 4
2005-2013 Microchip Technology Inc.
MCP2030
AC Characteristics (Continued)
Electrical Specifications:
Standard Operating Conditions (unless otherwise stated)
Supply Voltage
2.0V
V
DD
3.6V
Operating temperature
-40°C
T
A
+85°C
LCCOM connected to V
SS
LC Signal Input
Sinusoidal 300 mV
PP
Carrier Frequency
125 kHz
LCCOM connected to V
SS
Parameters
Demodulator Discharge Time (delay time
of demodulated output to fall)
Sym.
T
DF
Min.
—
Typ†
50
Max.
—
Units
Conditions
V
DD
= 3.0V
MOD depth setting = 33%
Input conditions:
Amplitude = 300 mV
PP
Modulation depth = 100%
V
DD
½3.0V.
Time is measured from 10% to
90% of amplitude
V
DD
½3.0V
Time is measured from 10% to 90% of
amplitude
s
Rise time of LFDATA
Fall time of LFDATA
TR
LFDATA
TF
LFDATA
—
—
0.5
0.5
—
—
s
s
ms
ms
AGC stabilization time
(T
AGC +
T
PAGC
)
AGC initialization time
High time after AGC initialization time
Gap time after AGC stabilization time
Time element of pulse
Time from exiting Sleep or POR to being
ready to receive signal
Minimum time AGC level must be held
after receiving AGC Preserve command
Internal RC oscillator frequency
Inactivity timer time-out
Alarm timer time-out
LC Pin Input Resistance
for
LCX, LCY, LCZ pins
LC Pin Input Parasitic Capacitance
for
LCX, LCY, LCZ pins
Minimum output enable filter high time
OEH (Bits Config0<8:7>)
01
= 1 ms
10
= 2 ms
11
= 4 ms
00
= Filter Disabled
Minimum output enable filter low time
OEL (Bits Config0<6:5>)
00
= 1 ms
01
= 1 ms
10
= 2 ms
11
= 4 ms
Maximum output enable filter period
OEH
01
01
01
01
10
10
10
10
11
11
11
11
00
OEL
00
01
10
11
00
01
10
11
00
01
10
11
XX
*
†
1:
2:
T
OEH
1 ms
1 ms
1 ms
1 ms
2 ms
2 ms
2 ms
2 ms
4 ms
4 ms
4 ms
4 ms
T
OEL
1 ms
1 ms
2 ms
4 ms
1 ms
1 ms
2 ms
4 ms
1 ms
1 ms
2 ms
4 ms
T
STAB
T
AGC
T
PAGC
T
GAP
T
E
T
RDY
T
PRES
F
OSC
T
INACT
T
ALARM
R
IN
4
—
—
200
100
—
5*
27
13.5
27
—
—
3.5
62.5
—
—
—
—
32
16
32
800*
24*
—
—
—
—
—
50*
—
35.5
17.75
35.5
—
—
s
s
s
ms
ms
kHz
ms
ms
k
pF
Minimum pulse width
AGC level must not change more than 10%
during T
PRES
.
Internal clock trimmed at 32 kHz during test
512 cycles of RC oscillator @ F
OSC
1024 cycles of RC oscillator @ F
OSC
LCCOM grounded, V
DD
= 3V,
F
CARRIER
= 125 kHz.
LCCOM grounded, V
DD
= 3V,
F
CARRIER
= 125 kHz.
RC oscillator = F
OSC
(see F
OSC
specification
for variations).
Viewed from the pin input:
(Note 1)
C
IN
—
T
OEH
32 (~1 ms)
64 (~2 ms)
128 (~4 ms)
—
T
OEL
32 (~1 ms)
32 (~1 ms)
64 (~2 ms)
128 (~4 ms)
T
OET
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
96 (~3 ms)
96 (~3 ms)
128 (~4 ms)
192 (~6 ms)
128 (~4 ms)
128 (~4 ms)
160 (~5 ms)
250 (~8 ms)
192 (~6 ms)
192 (~6 ms)
256 (~8 ms)
320 (~10 ms)
—
clock
count
—
—
—
—
—
—
—
—
clock
count
—
—
—
—
—
—
—
—
clock
count
RC oscillator = F
OSC
Viewed from the pin input:
(Note 2)
RC oscillator = F
OSC
=
=
=
=
=
=
=
=
=
=
=
=
(Filter 1)
(Filter 1)
(Filter 2)
(Filter 3)
(Filter 4)
(Filter 4)
(Filter 5)
(Filter 6)
(Filter 7)
(Filter 7)
(Filter 8)
(Filter 9)
= Filter Disabled
LFDATA output appears as long as input
signal level is greater than V
SENSE
.
Note
Parameter is characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Required output enable filter high time must account for input path analog delays (= T
OEH
- T
DR
+ T
DF
).
Required output enable filter low time must account for input path analog delays (= T
OEL
+ T
DR
- T
DF
).
2005-2013 Microchip Technology Inc.
DS21981B-page 5
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