74ALVCH16823
Rev. 3 — 1 February 2018
18-bit bus-interface D-type flip-flop with reset and enable;
3-state
Product data sheet
1
General description
The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring separate D-type inputs
for each flip-flop and 3-state outputs for bus oriented applications. Incorporates bushold
data inputs which eliminate the need for external pull-up resistors to hold unused inputs.
The 74ALVCH16823 consists of two sections of nine edge-triggered flip-flops. A clock
(nCP) input, an output-enable (nOE) input, a master reset (nMR) input and a clock-
enable (nCE) input are provided for each total 9-bit section.
With the clock-enable (nCE) input LOW, the D-type flip-flops will store the state of
their individual nDn-inputs that meet the set-up and hold time requirements on the
LOW-to-HIGH nCP transition. Taking nCE HIGH disables the clock buffer, thus latching
the outputs. Taking the master reset (nMR) input LOW causes all the nQn outputs to go
LOW independently of the clock.
When nOE is LOW, the contents of the flip-flops are available at the outputs. When the
nOE is HIGH, the outputs go to the high impedance OFF-state. Operation of the nOE
input does not affect the state of flip-flops.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic
level.
2
Features and benefits
•
•
•
•
•
•
•
•
•
•
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
Current drive ± 24 mA at 3.0 V
MULTIBYTE flow-through standard pin-out architecture
Low inductance multiple V
CC
and GND pins for minimum noise and ground bounce
Output drive capability 50 Ω transmission lines at 85°C
All data inputs have bushold
Complies with JEDEC standard no. 8-1A
Complies with JEDEC standards:
–
JESD8-5 (2.3 V to 2.7 V)
–
JESD8B/JESD36 (2.7 V to 3.6 V)
•
ESD protection:
–
HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V
–
CDM JESD22-C101E exceeds 1000 V
Nexperia
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
74ALVCH16823
3
Ordering information
Package
Temperature range Name
Description
Version
−40 °C to +85 °C
TSSOP56
plastic thin shrink small outline package; 56 leads; SOT364-1
body width 6.1 mm
Table 1. Ordering information
Type number
74ALVCH16823DGG
4
Functional diagram
2MR
1MR
1OE
2OE
28
1
2
27
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
56
29
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1CP
2CP
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
2CE
1CE
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
30
55
1OE
1MR
1CE
1CP
2OE
2MR
2CE
2CP
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2
1
55
56
27
28
30
29
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
EN1
R2
G3
3C4
EN5
R6
G7
7C8
4D
1,2
3
5
6
8
9
10
12
13
14
8D
5,6
15
16
17
19
20
21
23
24
26
001aad242
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
aaa-028141
Figure 1. Logic symbol
V
CC
Figure 2. IEC logic symbol
data input
to internal circuit
001aad245
Figure 3. Bushold circuit (one data input)
74ALVCH16823
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 1 February 2018
2 / 18
Nexperia
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
74ALVCH16823
5.2 Pin description
Table 2. Pin description
Symbol
1D0, 1D1, 1D2, 1D3, 1D4,
1D5, 1D6, 1D7, 1D8
1Q0, 1Q1, 1Q2, 1Q3, 1Q4,
1Q5, 1Q6, 1Q7, 1Q8
2D0, 2D1, 2D2, 2D3, 2D4,
2D5, 2D6, 2D7, 2D8
2Q0, 2Q1, 2Q2, 2Q3, 2Q4,
2Q5, 2Q6, 2Q7, 2Q8
1MR, 2MR
1OE, 2OE
1CP, 2CP
1CE, 2CE
GND
V
CC
Pin
54, 52, 51, 49, 48,
47, 45, 44, 43
3, 5, 6, 8, 9,
10, 12, 13, 14
42, 41, 40, 38, 37,
36, 34, 33, 31
15, 16, 17, 19, 20,
21, 23, 24, 26
1, 28
2, 27
56, 29
55, 30
4, 11, 18, 25,
32, 39, 46, 53
7, 22, 35, 50
Description
data inputs
data outputs
data inputs
data outputs
master reset inputs (active-LOW)
output enable inputs (active LOW)
clock pulse inputs (active rising edge)
clock enable inputs (active-LOW)
ground (0 V)
supply voltage
6
Functional description
[1]
Table 3. Function table
Operating mode
clear
load and read data
hold
disable outputs
Input
nOE
L
L
L
L
L
H
nMR
L
H
H
H
H
X
nCE
X
L
L
L
H
X
nCP
X
↑
↑
L
X
X
nDn
X
h
l
X
X
X
Output
nQn
L
H
L
NC
NC
Z
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
NC = no change;
X = don’t care;
Z = high-impedance OFF-state;
74ALVCH16823
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 1 February 2018
5 / 18
瑞萨MCU/MPU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
