Data Processing....................................................................................................................................................................... 26
5.0
Configuration and Status Registers ......................................................................................................................................... 41
6.0
Application Information ............................................................................................................................................................ 56
Packaging Information ............................................................................................................................................................. 63
The Microchip Web Site ....................................................................................................................................................................... 69
Customer Change Notification Service ................................................................................................................................................ 69
Customer Support ................................................................................................................................................................................ 69
Product Identification System .............................................................................................................................................................. 70
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DS40001778B-page 2
2015 Microchip Technology Inc.
MRF39RA
1.0
OVERVIEW
The MRF39RA is a single-chip integrated circuit
ideally suited for today’s high-performance ISM band
RF applications. The MRF39RA’s advanced features
set, including state-of-the-art packet engine, greatly
simplifies system design while the high level of
integration reduces the external bill of materials (BOM)
to a handful of passive decoupling and matching
components. It is intended for use as a
high-performance, low-cost FSK and OOK RF receiver
for robust frequency agile RF links, and where stable
and constant RF performance is required over the full
operating range of the device down to 1.8V.
The MRF39RA is intended for applications over a wide
frequency range, including the 433 MHz and 868 MHz
European and 902-928 MHz North American ISM
bands. Coupled with a very aggressive sensitivity, the
advanced system features of the MRF39RA include a
66-byte RX FIFO, configurable automatic packet
handler, Listen mode, temperature sensor and
configurable DIOs, which greatly enhance system
flexibility
while
significantly
reducing
MCU
requirements at the same time.
The MRF39RA complies with both ETSI and FCC
regulatory requirements and is available in a 5 x 5 mm
24-lead QFN package.
FIGURE 1-1:
SIMPLIFIED BLOCK DIAGRAM
VBAT1&2
VR_ANA
VR_DIG
RC
Oscillator
Modulators
Demodulator &
Bit Synchronizer
Decimation and
& Filtering
RESET
Power Distribution System
LNA
Single to
Differential
Mixers
RFIN
Control Registers - Shift Registers - SPI Interface
RSSI
Division by
2, 4 or 6
AFC
Packet Engine & 66 Bytes FIFO
SPI
GND
DIO0
DIO1
DIO2
DIO3
DIO4
Tank
Inductor
NC
NC
NC
Loop
Filter
Frac-N PLL
Synthesizer
XO
32 MHz
DIO5
XTAL
Frequency Synthesis
Receiver Blocks
Control Blocks
GND
Primarily Analog
Primarily Digital
2015 Microchip Technology Inc.
DS40001778B-page 3
MRF39RA
Table 1-1
lists the MRF39RA pinouts.
TABLE 1-1:
Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
MRF39RA PINOUTS
Name
GROUND
VBAT1
VR_ANA
VR_DIG
XTA
XTB
RESET
DIO0
DIO1/DCLK
DIO2/DATA
DIO3
DIO4
DIO5
VBAT2
GND
SCK
MISO
MOSI
NSS
NC
GND
RFIN
GND
NC
NC
—
—
—
—
I/O
I/O
I/O
I/O
O
O
I/O
I/O
I/O
—
—
I
O
I
I
—
—
I
—
—
—
Type
Exposed Ground Pad
Supply Voltage
Regulated Supply Voltage for Analogue Circuitry
Regulated Supply Voltage for Digital Blocks
XTAL Connection
XTAL Connection
Reset Trigger Input
Digital I/O; Software Configured
Digital Output; Software Configured
Digital Output; Software Configured
Digital I/O; Software Configured
Digital I/O; Software Configured
Digital I/O; Software Configured
Supply Voltage
Ground
SPI Clock Input
SPI Data Output
SPI Data Input
SPI Chip Select Input
Do not connect
Ground
RF Input
Ground
Do not connect
Do not connect
Description
DS40001778B-page 4
2015 Microchip Technology Inc.
MRF39RA
2.0
DEVICE DESCRIPTION
FIGURE 2-1:
TCXO CONNECTION
MRF39RA
This section describes in detail the architecture of the
MRF39RA low-power, highly integrated receiver.
2.1
Power Supply Strategy
XTA
XTB
NC
OP
V
CC
GND
C
D
V
CC
The MRF39RA employs an advanced power supply
scheme,
which
provides
stable
operating
characteristics over the full temperature and voltage
range of operation.
The MRF39RA can be powered from any low-noise
voltage source via pins VBAT1 and VBAT2. As
suggested in the reference design, decoupling
capacitors must be connected on VR_DIG and
VR_ANA pins to ensure a correct operation of the
built-in voltage regulators.
TCXO
32 MHZ
2.2
Low Battery Detector
2.3.2
CLKOUT OUTPUT
A low battery detector is also included enabling the
generation of an interrupt signal in response to passing
a programmable threshold adjustable through the
RegLowBat register. The interrupt signal can be
mapped to any of the DIO pins through the
programming of RegDioMapping.
2.3
Frequency Synthesis
The LO generation on the MRF39RA is based on a
state-of-the-art fractional-N PLL. The PLL is fully
integrated with automatic calibration.
2.3.1
REFERENCE OSCILLATOR
The crystal oscillator is the main timing reference of the
MRF39RA. It is used as a reference for the frequency
synthesizer and as a clock for the digital processing.
The XO start-up time, TS_OSC, depends on the actual
XTAL being connected on pins XTA and XTB. When
using the built-in sequencer, the MRF39RA optimizes
the start-up time and automatically triggers the PLL
when the XO signal is stable. To manually control the
start-up time, the user must either wait for TS_OSC
max, or monitor the signal CLKOUT, which is only
made available on the output buffer when a stable XO
oscillation is achieved.
An external clock can be used to replace the crystal
oscillator, for instance a tight tolerance TCXO. To do
this, bit 4 at address 0x59 must be set to ‘1’, and the
external clock has to be provided on XTA (pin 4). XTB
(pin 5) must be left open. The peak-peak amplitude of
the input signal must never exceed 1.8V. Consult the
TCXO supplier for an appropriate value of decoupling
capacitor, CD.
Figure 2-1
shows the TCXO connection.
The reference frequency, or a fraction of it, can be
provided on DIO5 (pin 12) by modifying bits ClkOut in
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