UM10540
NVT2001GM and NVT2002DP demo boards
Rev. 1 — 7 March 2012
User manual
Document information
Info
Keywords
Content
NVT, voltage translator, level translator, level shift, passive voltage
translator, passive level translator, passive level shift, I2C-bus, SMBus,
SPI, NVT2001, NVT2002
NXP Voltage Translators (NVT) are used in bidirectional signaling voltage
level translation applications for I/O buses with incompatible logic levels.
The NVT2001 and NVT2002 are single- and dual-channel voltage
translators, operational from 1.0 V to 3.6 V at V
CC(A)
(low voltage side) and
1.8 V to 5.5 V at V
CC(B)
(high voltage side) without direction control for
open-drain or push-pull I/O devices.
Abstract
NXP Semiconductors
UM10540
NVT2001GM and NVT2002DP demo boards
Revision history
Rev
v.1
Date
20120307
Description
user manual; initial release
Contact information
For more information, please visit:
http://www.nxp.com
For sales office addresses, please send an email to:
salesaddresses@nxp.com
UM10540
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1 — 7 March 2012
2 of 7
NXP Semiconductors
UM10540
NVT2001GM and NVT2002DP demo boards
1. Introduction
The NVT2001GM (OM13315) and NVT2002DP (OM13318) demo boards are designed to
evaluate the NXP 1-channel or 2-channel bidirectional voltage level translators. The demo
boards interface between device I/Os operating at different voltage levels. Since the
NVT2001GM and NVT2002DP devices are passive devices, pull-up resistors may be
needed depending on the I/O interface type (totem pole or open-drain), difference in
translation voltage, and the translation direction (high to low voltage, low to high voltage,
or bidirectional). The NVT2001GM and NVT2002DP devices allow translations between
any voltages from 1.0 V to 5.5 V.
Please refer to NVT2001/NVT2002 data sheet (Ref.
1)
and application note
AN11127
(Ref.
2)
for more detailed information.
019aac711
019aac712
a. NVT2001GM (OM13315)
Fig 1.
Bidirectional voltage level translators demo boards
b. NVT2002DP (OM13318)
UM10540
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1 — 7 March 2012
3 of 7
NXP Semiconductors
UM10540
NVT2001GM and NVT2002DP demo boards
2. Hardware description
2.1 Schematic
The demo boards contain footprints for the NVT2001GM and NVT2002DP devices, where
the jumpers, headers, and passive components are shared. The NVT2001GM and
NVT2002DP demo board schematic is shown in
Figure 2.
Pins 2 and 3 on J1 must be
shorted to enable the part. Pins 4 and 1 on J3 are power and GND for the low voltage
side. Pins 4 and 1 on J4 are power and GND for the high voltage side. All Bn I/O pins on
the right side have 10 kΩ pull-up resistors to VREFB and all An I/O pins on the left side
have 10 kΩ pull-up resistors to VREFA through jumper J2. A shunt needs to be installed
at J2 if VREFB
−
VREFA < 1 V. If VREFB
−
VREFA
≥
1 V, then J2 should be open and
resistors R2 and R3 must be removed. If they are not removed, then a resistive path
exists between the A-side I/Os that can impact the efficiency and signal integrity of the
solution.
Jumper:
ON: if VREFB − VREFA < 1 V
(populated 10 kΩ pull-up resistors)
OFF: if VREFB − VREFA ≥ 1 V
(do not populate 10 kΩ pull-up resistors)
low voltage
A-side
J3
J1
2-3: switch enable
1-2: switch disable
high voltage
B-side
J4
NVT2002DP
8
7
EN
VREFB
EN_Vb
1
J2
JP
VREFA 2
A1
3
A2
4
U1
VREFA
4
A1
3
A2
2
GND
1
header 1
×
4
2
1
2
3
R1
200 kΩ
R3 10 kΩ
R2 10 kΩ
1
GND
C1
0.1 μF
R5 10 kΩ
R4 10 kΩ
B1
6
B2
5
VREFB
4
B1
3
B2
2
GND
1
header 1
×
4
NVT2001GL
VREFA 2
A1
6
5
3
U2
EN
VREFB
B1
EN_Vb
1
4
GND
002aag940
Fig 2.
NVT2001GM and NVT2002DP demo board schematic
UM10540
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1 — 7 March 2012
4 of 7
NXP Semiconductors
UM10540
NVT2001GM and NVT2002DP demo boards
2.2 Jumper and header functions
The functions of the jumpers and headers on these demo boards are shown in
Table 1.
Table 1.
J1 (3-pin)
Header descriptions for NVT2001GM (OM13315) and NVT2002DP (OM13318) demo boards
Function
Device switch enable or disable
control
Connects 10 kΩ pull-up resistors to
VREFA on low voltage side for
VREFB
−
VREFA < 1 V
Low voltage VREFA, GND and
An I/O signal connect pins
Notes
Short pins 2 and 3 to enable the NVT2001GM or NVT2002DP
device (default). When pins 1 and 2 are shorted, the device is
disabled.
Short pins 1 and 2 to connect 10 kΩ pull-up resistors to VREFA
on low voltage side (default).
Remark:
Pins 1 and 2 must be open and 10 kΩ pull-up resistors
must be removed when VREFB
−
VREFA
≥
1 V.
Pin 1 = VREFA: low voltage power.
Pin 4 = GND: low voltage ground.
A1 is low voltage signal for NVT2001GM.
A[1:2] are low voltage signals for NVT2002DP.
J4 (4-pin)
High voltage VREFB, GND and
Bn I/O signal connect pins
Pin 1 = VREFB: high voltage power.
Pin 4 = GND: high voltage ground.
B1 is high voltage signal for NVT2001GM.
B[1:2] are high voltage signals for NVT2002DP.
Jumper/header
J2 (2-pin)
J3 (4-pin)
3. Abbreviations
Table 2.
Acronym
I
2
C-bus
I/O
SMBus
SPI
Abbreviations
Description
Inter-Integrated Circuit bus
Input/Output
System Management Bus
Serial Peripheral Interface
4. References
[1]
NVT2001; NVT2002, “Bidirectional voltage level translator for open-drain and
push-pull applications” —
Product data sheet; NXP Semiconductors;
www.nxp.com/documents/data_sheet/NVT2001_NVT2002.pdf
AN11127, “Bidirectional voltage level translators NVT20xx, PCA9306,
GTL2000, GTL2002, GTL2003, GTL2010” —
application note;
NXP Semiconductors;
www.nxp.com/documents/application_note/AN11127.pdf
[2]
UM10540
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1 — 7 March 2012
5 of 7
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