SSM3K35AFS
MOSFETs
Silicon N-Channel MOS
SSM3K35AFS
1. Applications
•
•
High-Speed Switching
Analog Switches
2. Features
(1)
(2)
1.2 V drive
Low drain-source on-resistance
: R
DS(ON)
= 9.0
Ω
(max) (@V
GS
= 1.2 V, I
D
= 10 mA)
R
DS(ON)
= 3.1
Ω
(max) (@V
GS
= 1.5 V, I
D
= 20 mA)
R
DS(ON)
= 2.4
Ω
(max) (@V
GS
= 1.8 V, I
D
= 150 mA)
R
DS(ON)
= 1.6
Ω
(max) (@V
GS
= 2.5 V, I
D
= 150 mA)
R
DS(ON)
= 1.1
Ω
(max) (@V
GS
= 4.5 V, I
D
= 150 mA)
3. Packaging and Pin Assignment
1: Gate
2: Source
3: Drain
SSM
Start of commercial production
©2016 Toshiba Corporation
1
2016-10
2017-02-17
Rev.3.0
SSM3K35AFS
4. Absolute Maximum Ratings (Note) (Unless otherwise specified, T
a
= 25
)
Characteristics
Drain-source voltage
Gate-source voltage
Drain current
Drain current (pulsed)
Power dissipation
Power dissipation
Channel temperature
Storage temperature
(Note 1)
(Note 1)
(Note 2)
(Note 3)
T
ch
T
stg
Symbol
V
DSS
V
GSS
I
D
I
DP
P
D
Rating
20
±10
250
600
150
500
150
-55 to 150
mW
mA
Unit
V
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 1: Ensure that the channel temperature does not exceed 150
.
Note 2: Mounted on an FR4 board (25.4 mm
×
25.4 mm
×
1.6 mm, Cu pad: 0.36 mm
2
×
3)
Note 3: Mounted on an FR4 board (25.4 mm
×
25.4 mm
×
1.6 mm, Cu pad: 645 mm
2
)
Note:
Note:
Note:
The MOSFETs in this device are sensitive to electrostatic discharge. When handling this device, the worktables,
operators, soldering irons and other objects should be protected against anti-static discharge.
The channel-to-ambient thermal resistance, R
th(ch-a)
, and the drain power dissipation, P
D
, vary according to
the board material, board area, board thickness and pad area. When using this device, be sure to take heat
dissipation fully into account.
©2016 Toshiba Corporation
2
2017-02-17
Rev.3.0
SSM3K35AFS
5. Electrical Characteristics
5.1. Static Characteristics (Unless otherwise specified, T
a
= 25
)
Characteristics
Gate leakage current
Drain cut-off current
Drain-source breakdown voltage
Gate threshold voltage
Drain-source on-resistance
(Note 1)
(Note 2)
Symbol
I
GSS
I
DSS
V
th
Test Condition
V
GS
=
±10
V, V
DS
= 0 V
V
DS
= 20 V, V
GS
= 0 V
V
DS
= 10 V, I
D
= 100
µA
I
D
= 150 mA, V
GS
= 2.5 V
I
D
= 150 mA, V
GS
= 1.8 V
I
D
= 20 mA, V
GS
= 1.5 V
I
D
= 10 mA, V
GS
= 1.2 V
I
D
= 150 mA, V
GS
= 4.5 V,
T
j
= 125
Forward transfer admittance
Reverse drain current (pulsed)
(Note 2)
(Note 2)
|Y
fs
|
I
DRP
V
DS
= 10 V, I
D
= 150 mA
Min
20
0.35
Typ.
0.75
1.1
1.4
1.7
2.4
1.25
0.5
Max
±1
1
1.0
1.1
1.6
2.4
3.1
9.0
2.5
600
S
mA
V
V
Ω
Unit
µA
V
(BR)DSS
I
D
= 1 mA, V
GS
= 0 V
R
DS(ON)
I
D
= 150 mA, V
GS
= 4.5 V
Note 1: Let V
th
be the voltage applied between gate and source that causes the drain current (I
D
) to below (100
µA
for
this device). Then, for normal switching operation, V
GS(ON)
must be higher than V
th
, and V
GS(OFF)
must be
lower than V
th
. This relationship can be expressed as: V
GS(OFF)
< V
th
< V
GS(ON)
.
Take this into consideration when using the device.
Note 2: Pulse measurement.
5.2. Dynamic Characteristics (Unless otherwise specified, T
a
= 25
)
Characteristics
Input capacitance
Reverse transfer capacitance
Output capacitance
Switching time (turn-on delay time)
Switching time (rise time)
Switching time (turn-off delay time)
Switching time (fall time)
Symbol
C
iss
C
rss
C
oss
t
d(on)
t
r
t
d(off)
t
f
V
DD
= 10 V, I
D
= 75 mA,
V
GS
= 0 to 4.5 V, R
G
= 10
Ω
Test Condition
V
DS
= 10 V, V
GS
= 0 V,
f = 1 MHz
Min
Typ.
18
5
6
2
2
6.5
5.5
Max
36
10
12
ns
Unit
pF
5.3. Switching Time Test Circuit
Fig. 5.3.1 Switching Time Test Circuit
Fig. 5.3.2 Input Waveform/Output Waveform
©2016 Toshiba Corporation
3
2017-02-17
Rev.3.0
SSM3K35AFS
5.4. Gate Charge Characteristics (Unless otherwise specified, T
a
= 25
)
Characteristics
Total gate charge (gate-source plus gate-drain)
Gate-source charge 1
Gate-drain charge
Symbol
Q
g
Q
gs1
Q
gd
Test Condition
V
DD
= 10 V, I
D
= 200 mA,
V
GS
= 4.5 V
Min
Typ.
0.34
0.09
0.16
Max
Unit
nC
5.5. Source-Drain Characteristics (Unless otherwise specified, T
a
= 25
)
Characteristics
Diode forward voltage
(Note 1)
Symbol
V
DSF
Test Condition
I
D
= -150 mA, V
GS
= 0 V
Min
Typ.
-0.8
Max
-1.2
Unit
V
Note 1: Pulse measurement.
6. Marking
Fig. 6.1 Marking
©2016 Toshiba Corporation
4
2017-02-17
Rev.3.0
SSM3K35AFS
7. Characteristics Curves (Note)
Fig. 7.1 I
D
- V
DS
Fig. 7.2 I
D
- V
GS
Fig. 7.3 R
DS(ON)
- V
GS
Fig. 7.4 R
DS(ON)
- V
GS
Fig. 7.5 R
DS(ON)
- I
D
Fig. 7.6 R
DS(ON)
- T
a
©2016 Toshiba Corporation
5
2017-02-17
Rev.3.0
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