PTN3381B
Enhanced performance HDMI/DVI level shifter with voltage
regulator, dongle detect support and active DDC buffer
Rev. 2 — 15 October 2010
Product data sheet
1. General description
The PTN3381B is a high-speed level shifter device which converts four lanes of low-swing
AC-coupled differential input signals to DVI v1.0 and HDMI v1.3a compliant open-drain
current-steering differential output signals, up to 1.65 Gbit/s per lane. Each of these lanes
provides a level-shifting differential buffer to translate from low-swing AC-coupled
differential signaling on the source side, to TMDS-type DC-coupled differential
current-mode signaling terminated into 50
Ω
to 3.3 V on the sink side. Additionally, the
PTN3381B provides a single-ended active buffer for voltage translation of the HPD signal
from 5 V on the sink side to 3.3 V on the source side and provides a channel with active
buffering and level shifting of the DDC channel (consisting of a clock and a data line)
between 3.3 V source-side and 5 V sink-side. The DDC channel is implemented using
active I
2
C-bus buffer technology providing capacitive isolation, redriving and level shifting
as well as disablement (isolation between source and sink) of the clock and data lines.
To provide the highest level of integration in external adapter (or: dongle) applications,
PTN3381B includes an onboard 5 V DC regulator. Its output is designed to provide the
required 5 V power supply to the DVI or HDMI connector, thereby eliminating the need for
a separate external regulator. The on-board regulator needs only two external capacitors
to operate, and its output is active whenever a valid 3.3 V is applied to the PTN3381B V
DD
pins.
The low-swing AC-coupled differential input signals to the PTN3381B typically come from
a display source with multi-mode I/O, which supports multiple display standards, e.g.,
DisplayPort, HDMI and DVI. While the input differential signals are configured to carry DVI
or HDMI coded data, they do not comply with the electrical requirements of the DVI v1.0
or HDMI v1.3a specification. By using PTN3381B, chip set vendors are able to implement
such reconfigurable I/Os on multi-mode display source devices, allowing the support of
multiple display standards while keeping the number of chip set I/O pins low. See
Figure 1.
The PTN3381B main high-speed differential lanes feature low-swing self-biasing
differential inputs which are compliant to the electrical specifications of
DisplayPort
Standard v1.1
and/or
PCI Express Standard v1.1,
and open-drain current-steering
differential outputs compliant to DVI v1.0 and HDMI v1.3a electrical specifications. The
I
2
C-bus channel actively buffers as well as level-translates the DDC signals for optimal
capacitive isolation. Its I
2
C-bus control block also provides for optional software HDMI
dongle detect by issuing a predetermined code sequence upon a read command to an
I
2
C-bus specified address. The PTN3381B also supports power-saving modes in order to
minimize current consumption when no display is active or connected.
The PTN3381B is a fully featured HDMI as well as DVI level shifter. It is functionally
equivalent to PTN3361B but provides an onboard 5 V regulator.
NXP Semiconductors
PTN3381B
Fully integrated HDMI/DVI level shifter
PTN3381B is powered from a single 3.3 V power supply consuming a small amount of
power (100 mW typical without load at 5 V regulator output) and is offered in a 48-terminal
HVQFN48 package.
MULTI-MODE DISPLAY SOURCE
OE_N
reconfigurable I/Os
PCIe PHY ELECTRICAL
TMDS
coded
data
PCIe
output buffer
TX
FF
TX
TMDS
coded
data
PCIe
output buffer
TX
FF
TX
TMDS
coded
data
PCIe
output buffer
TX
FF
TX
TMDS
clock
pattern
PCIe
output buffer
TX
FF
TX
AC-coupled
differential pair
clock
CLOCK LANE
OUT_D1+
OUT_D1−
IN_D1+
IN_D1−
AC-coupled
differential pair
TMDS data
DATA LANE
IN_D2+
IN_D2−
OUT_D2+
OUT_D2−
AC-coupled
differential pair
TMDS data
IN_D3+
DATA LANE
IN_D3−
OUT_D3+
OUT_D3−
AC-coupled
differential pair
TMDS data
IN_D4+
DATA LANE
IN_D4−
OUT_D4+
OUT_D4−
PTN3381B
0 V to 3.3 V
HPD_SOURCE
DDC_EN
(0 V to 3.3 V)
DDET
HPD_SINK
0 V to 5 V
3.3 V
3.3 V
3.3 V
5V
SCL_SOURCE
3.3 V
DDC I/O
(I
2
C-bus)
CONFIGURATION
SDA_SOURCE
SCL_SINK
5V
SDA_SINK
V5OUT
5 V
DC
out
002aae076
Remark:
TMDS clock and data lanes can be assigned arbitrarily and interchangeably to D[4:1].
Fig 1.
Typical application system diagram
PTN3381B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 15 October 2010
DVI/HDMI CONNECTOR
2 of 30
NXP Semiconductors
PTN3381B
Fully integrated HDMI/DVI level shifter
2. Features and benefits
2.1 High-speed TMDS level shifting
Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and
HDMI v1.3a compliant open-drain current-steering differential output signals
Pin-programmable pre-emphasis feature
TMDS level shifting operation up to 1.65 Gbit/s per lane (165 MHz character clock)
TMDS level shifting operation up to 2.25 Gbit/s per lane (225 MHz character clock)
using pre-emphasis feature
Integrated 50
Ω
termination resistors for self-biasing differential inputs
Back-current safe outputs to disallow current when device power is off and monitor is
on
Disable feature to turn off TMDS inputs and outputs and to enter low-power state
2.2 DDC level shifting
Integrated DDC buffering and level shifting (3.3 V source to 5 V sink side)
Rise time accelerator on sink-side DDC ports
0 Hz to 400 kHz I
2
C-bus clock frequency
Back-power safe sink-side terminals to disallow backdrive current when power is off or
when DDC is not enabled
2.3 HDMI dongle detect support
Incorporates I
2
C slave ROM
Responds to DDC read to address 81h with predetermined byte sequence
Feature enabled by pin DDET (must be enabled for correct operation in accordance
with DisplayPort interoperability guideline)
2.4 HPD level shifting
HPD non-inverting level shift from 0 V on the sink side to 0 V on the source side, or
from 5 V on the sink side to 3.3 V on the source side
Integrated 200 kΩ pull-down resistor on HPD sink input guarantees ‘input LOW’ when
no display is plugged in
Back-power safe design on HPD_SINK to disallow backdrive current when power is off
2.5 5 V DC voltage regulator
Generates 5 V for the DVI/HDMI connector from the 3.3 V DP_PWR pin supplied by
the DisplayPort connector
Supports up to 75 mA of load current with an accuracy of
±300
mV
Only two external capacitors required
Eliminates need for an external 5 V regulator in dongle applications
Back drive protection on 5 V output
Short-circuit protection
Overcurrent protection
PTN3381B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 15 October 2010
3 of 30
NXP Semiconductors
PTN3381B
Fully integrated HDMI/DVI level shifter
2.6 General
Power supply 3.3 V
±
10 %
ESD resilience to 4 kV HBM, 1 kV CDM
Support for optional HDMI dongle detection via DDC/I
2
C-bus channel
Power-saving modes (using output enable)
Back-current-safe design on all sink-side main link, DDC and HPD terminals
Transparent operation: no re-timing or software configuration required
3. Applications
DisplayPort to HDMI adapters
DisplayPort to DVI adapters required to drive long cables
4. Ordering information
Table 1.
Ordering information
Package
Name
PTN3381BBS
HVQFN48
Description
Version
plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; SOT619-1
body 7
×
7
×
0.85 mm
Type number
PTN3381B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 15 October 2010
4 of 30
NXP Semiconductors
PTN3381B
Fully integrated HDMI/DVI level shifter
5. Functional diagram
OE_N
input bias
enable
50
Ω
50
Ω
PTN3381B
OUT_D4+
OUT_D4−
IN_D4+
IN_D4−
input bias
enable
50
Ω
50
Ω
enable
OUT_D3+
OUT_D3−
IN_D3+
IN_D3−
input bias
enable
50
Ω
50
Ω
enable
OUT_D2+
OUT_D2−
IN_D2+
IN_D2−
input bias
enable
50
Ω
50
Ω
enable
OUT_D1+
OUT_D1−
IN_D1+
IN_D1−
enable
HPD level shifter
HPD_SOURCE
(0 V to 3.3 V)
DDC_EN (0 V to 3.3 V)
SCL_SOURCE
SDA_SOURCE
DDET
CP
Creg(ext)
200 kΩ
HPD_SINK
(0 V to 5 V)
I
2
C-BUS
SLAVE
ROM
DDC BUFFER
AND
LEVEL SHIFTER
SCL_SINK
SDA_SINK
V5OUT
DC REGULATOR
Co(reg)
CN
002aae077
Fig 2.
Functional diagram of PTN3381B
PTN3381B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 15 October 2010
5 of 30
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